In this study, a physics-based compact model for high speed buffer layer insulated gate bipolar transistor (IGBT) is proposed. The model utilizes the 1-D Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink. Based on the improved understanding on the inductive switching behavior of high speed buffer layer IGBT, the ADE is solved for all injection levels instead of high-level injection only as usually done. Assuming high-level injection condition in the buffer layer, the excess carrier transport, redistribution and recombination in the buffer layer are redescribed. Moreover, some physical characteristics such as the low conductivity of N-base at turn-on transient and free holes appeared in the depletion layer during turn-off process are also considered in the model. Finally, The double-pulse switching tests for a commercial field stop (FS) IGBT and a light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) are used to validate the proposed model. The simulation results are compared with experiment results and good agreement is obtained.Index Terms-insulated gate bipolar transistor (IGBT), power semiconductor modeling, field stop (FS) IGBT, light punchthrough (LPT) carrier stored trench bipolar transistor (CSTBT), physics-based IGBT model.

Purpose The purpose of this paper is to present a failure analysis of the solder layer in a Darlington power transistor in a TO-3 package. Design/methodology/approach A failed Darlington power transistor in a TO-3 package was examined by different kinds of failure analysis techniques. At first, internal gas analysis was conducted to measure the atmosphere. Then, scanning acoustic microscopy (SAM) was performed to check the quality of the solder layers in the failed device, and the failure location was determined in the solder layer between chip and substrate. Next, the failed device was decapped to observe the defects. After removing the chip from the substrate, energy dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) were applied and the main elemental composition of the solder layer was identified. Findings Internal gas analysis indicated that the moisture and oxygen contents exceeded the allowed maximum value. Large areas of voids were found in the solder layer by SAM. The main elemental compositions of the solder layer were identified by scanning electron microscopy and EDS. Furthermore, the valences of the chemical components in the solder layer were identified by XPS. Except for the few simple substances of the initial solder material, the chemical formulae of oxidation products in the solder layer were deduced. In addition, the root causes are also discussed. Originality/value This paper focuses on the solder layer failure of a power transistor. Factors such as the presence of oxygen, voids and other factors, which can cause transistor damage, were comprehensively analyzed. The analysis process is worth learning from and the results can be used to improve the reliability of power devices in this kind of package.

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An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

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