Purpose The purpose of this paper is to present a failure analysis of the solder layer in a Darlington power transistor in a TO-3 package. Design/methodology/approach A failed Darlington power transistor in a TO-3 package was examined by different kinds of failure analysis techniques. At first, internal gas analysis was conducted to measure the atmosphere. Then, scanning acoustic microscopy (SAM) was performed to check the quality of the solder layers in the failed device, and the failure location was determined in the solder layer between chip and substrate. Next, the failed device was decapped to observe the defects. After removing the chip from the substrate, energy dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) were applied and the main elemental composition of the solder layer was identified. Findings Internal gas analysis indicated that the moisture and oxygen contents exceeded the allowed maximum value. Large areas of voids were found in the solder layer by SAM. The main elemental compositions of the solder layer were identified by scanning electron microscopy and EDS. Furthermore, the valences of the chemical components in the solder layer were identified by XPS. Except for the few simple substances of the initial solder material, the chemical formulae of oxidation products in the solder layer were deduced. In addition, the root causes are also discussed. Originality/value This paper focuses on the solder layer failure of a power transistor. Factors such as the presence of oxygen, voids and other factors, which can cause transistor damage, were comprehensively analyzed. The analysis process is worth learning from and the results can be used to improve the reliability of power devices in this kind of package.

Under the action of a complex and harsh working environment, the damage of the IGBT power module's packaging interconnection structure is the primary failure mode. The crack propagation and the bonding interface and the bond point shedding in the bonding wires will seriously affect the device's electrical interconnection function and heat dissipation ability, resulting in its performance degradation and failure. In this work, the formulation and application of a multiscale approach combined with a cohesive zone model (CZM) were proposed to investigate IGBT bonding wires' crack propagation. Firstly, the cohesive force model's principle considering fatigue damage accumulation is analyzed, and the degradation multiscale simulation method of the critical structure of the power module is studied. Secondly, further research on IGBT bonding wires' degradation behavior is carried out based on the macro and micro scales. The IGBT power module key package structure's defect evolution model is established to analyze the damage evolution process of the critical package structure. Finally, the accuracy of the model is verified by the experiment analysis. Such a multiscale, mechanism-based cohesive zone model offers a promising approach for modeling and understanding the rate-dependent fracture of IGBT bonding wire crack evolution.

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The reliability issue of IGBT is a concern for researchers given the critical role the device plays in the safety of operations of the converter system. The reliability of power devices can be estimated from the intermittent life test, which aims to simulate typical applications in power electronics in an accelerated manner to obtain lifetime data. However, the test is time-consuming, as testing conditions are not well considered and only rough provisions have been made in the current standards. Acceleration of the test by changing critical test conditions is controversial due to the activation of unexpected failure mechanisms. Therefore, full investigations were conducted on critical test conditions of intermittent life test. A design optimization process for IGBT intermittent life testing program was developed to save on test times without imposing additional failure mechanisms. The applicability of the process has been supported by a number of tests and failure analysis of the test results. The process proposed in this paper can guide the test process for other power semiconductors.