The connection of low power renewable energy sources, such as fuel cells, to the distribution generation system requires power electronics structures with high voltage gain, high capability to power processing and consequently, high levels of current flowing through the dc/dc converter. In this context, this study analyses how the parasitic resistances of the passive components and the load power demand affect the dc/dc converter voltage gain. Taking into account the mathematical model, the boundaries of operation of the Interleaved Boost with Voltage Multiplier converter is determined through a set of equations and by means of a graphical analysis. The theoretical analysis, simulations and experimental results are used to validate the proposed approach presented in this study.

This paper presents an adaptive powersharing methodology for management of dc microgrids powered by fuel cell (FC) and storage system (SS). In this context, the use of an adaptive k-sharing function in the control scheme is proposed to compensate the fast transients on the ac-side and manage the power sharing at steady-state regime between the FC and SS. The adaptive k-sharing is implemented with a low-pass filter transfer function for the FC and a complementary transfer function associated with the adaptive k-sharing gain for the SS. The proposed adaptive k-sharing function links the FC and the SS dynamics with the management of the dc microgrid, ensuring that the entire FC operation is performed in accordance with its operational limits. One of the main advantages of the proposed adaptive k-sharing is to reach high levels of stability and minimum disruptions on the FC terminals. To evaluate the feasibility of the proposed approach, we analyze the k-sharing behavior to determine the operational limits of the dc microgrid. Finally, to support the theoretical analysis we carried out a set of experimental results.

The connection of distributed generation systems powered by fuel cells (FCs) to the grid requires power electronics devices with high voltage gain, high capability of power processing and high levels of current absorbed from the direct current (dc) source. In this context, the authors propose the use of an interleaved boost with voltage multiplier (IBVM) converter connected to a FC and a voltage source inverter (VSI) to form a micro grid. To manage the power delivered by the FC in gridconnected operation, they propose two different control structures, mode 1 (FC cascade control) and mode 2 (controlling FC operating point). In mode 1, the dc-link voltage is adjusted by the dc/dc converter, while the injected current is controlled by the VSI. On the other hand, in mode 2, the VSI is responsible to keep the dc-link stable, while the dc/dc converter controls the current injected into the grid by means of the FC current reference. Since the VSI control structure has been exhaustively investigated in the literature, in this study, they evaluate the impact of the proposed control structures in the dc-side and also the IBVM efficiency. Finally, they conclude the study outlining the main points discussed.

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In this study, the authors propose a method to implement a low-cost hardware-in-the-loop (HIL) system for power converters and microgrids design, test and analysis. This approach uses a digital signal processor (DSP) Texas Instruments as the HIL core. All the differential equations of the power converters are solved in real-time by the DSP and displayed in the digital-to-analogue outputs. Three different converters are modelled in this study: boost converter, single-phase inverter connected to the grid and three-phase inverter connected to the grid. Experimental results are obtained and compared to the HIL response. These results were made triggering the real converter and the HIL with the same open-loop pulse width modulation signal, showing high fidelity between the digital models over the real systems. In a second moment, a microgrid is modelled in the proposed HIL and tested with a closed-loop controller. The experiments show that the proposed hardware supports time steps as low as 1 μs or 1 MHz update rate, depending on the model. The proposed technique has the potential to reduce testing time and cost, once commercial HIL devices such as Typhoon, dSPACE and RTDS have a significant cost, not affordable or available to all the research community