This paper presents research on modeling and simulation of the lag effect, which is one of the most important effects in a deep reactive ion etching (DRIE) process. From theoretical analysis and experimental investigation of the lag effect, it has been found that the shielding effect and flow change of reactive ions are two dominant factors. Based on our previous work on DRIE modeling, a modified model considering these two lag effect factors has been established, and a 2D DRIE simulator is developed according to this model. The simulation results were in good agreement with experiments.Corrections were made to this article on 8 November 2006. Reproduction of figure 1 with permission from the author, Dr Chung, was acknowledged and referencing of the figure was corrected. In addition textual references to two of Dr Chung's articles (reference [10] and new reference [13]) were corrected. The corrected electronic version is identical to the print version.

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Deep reactive ion etching (DRIE) technique is a new and powerful tool in Micro-Electro-Mechanical Systems (MEMS) fabrication. A 3-D DRIE simulation can help researcher understand the time-evolution of Bosch process used in DRIE. Due to the high complexity of the algorithm used in the simulation, it is necessary to develop an algorithm that can speedup the simulation. This paper presents a parallel implementation of the 3-D DRIE simulation based onmulti-core processor. The algorithm is based on data partition. We examine four different data partition strategies and find two-dimensional block-cyclic distribution can obtain perfect load balance. The experimental results show that the parallel algorithm obtains a substantial speedup over the serial algorithm on an Intel quad-core computer.

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