The conventional circuit model of a bit-stream adder based on sigma delta ( †/ modulation is improved with pipeline technology to make it work correctly at high frequencies. The integrated circuit (IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency. The IC is fabricated in TSMC's 0.18-m CMOS process. The chip area is 475 570 m 2 . A fully digital † signal generator is designed with a field programmable gate array to test the chip. Experimental results show that the chip meets the function and performance demand of the design, and the chip can work at a frequency of higher than 4 GHz. The noise performance of the adder is analyzed and compared with both theory and experimental results.

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A novel method to build an artificial neuron is presented. All the modules in the artificial neuron are bit-stream units based on direct Σ-Δ signal process. The fundamental modules used in bit-stream artificial neuron, i.e., adder, multiplier, activation function unit, were implemented in integrated circuit (IC) form or Field Programmable Gate Array (FPGA). The principle, the structure and the performance of the modules are discussed.

An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-m CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier's noise performance is also presented.