HfO 2 based high-permittivity gate dielectric has been introduced to CMOS logic device manufacturing since from 45nm node. However, these dielectrics are still under investigation and continuous optimization because of their relatively high oxygen vacancy concentration. Post Dielectric Annealing (PDA) after HK film may be a promising approach to reduce HK film trapped defect density and improve device performance as some literature reported recently. In the present work, different annealing conditions were applied on interface layer (IL)/HfO 2 stack films, including soak annealing, spike annealing, and flash lamp based Milli-Second Annealing (MSA). Both blanket wafer and MOSCAP wafer characterization results show post HK MSA is an effective method to repair HK intrinsic defect, like oxygen vacancy, while it also beneficial for improving the Si/IL, IL/HK interface quality. Keywords-HfO 2 , post HK annealing (PDA), MSA, oxygen vacancy, interface trapI.

In the present work, a novel RTON (Rapid Thermal Oxidation and Nitridation) was investigated as STI (Shallow Trench Isolation) liner dielectric in 45-nm CMOS. Compare with conventional ISSG (In-Situ Steam Generation) oxide, this RTON liner demonstrate better device performance for NMOS transistors both in long channel and short channel. It shown >4% Ioff/Ion improvement and exhibit more tighten SRAM standby leakage distribution. These performance gains can be explained by RTON liner contribution to NMOS channel tensile stress enhancement as well as its excellent capability to prevent channel doping diffusion.