A Novel Shallow Trench Isolation Liner Dielectric to Enhance NMOS Performance toward 45nm and Beyond

Abstract

In the present work, a novel RTON (Rapid Thermal Oxidation and Nitridation) was investigated as STI (Shallow Trench Isolation) liner dielectric in 45-nm CMOS. Compare with conventional ISSG (In-Situ Steam Generation) oxide, this RTON liner demonstrate better device performance for NMOS transistors both in long channel and short channel. It shown >4% Ioff/Ion improvement and exhibit more tighten SRAM standby leakage distribution. These performance gains can be explained by RTON liner contribution to NMOS channel tensile stress enhancement as well as its excellent capability to prevent channel doping diffusion.