Non-volatile memory (NVM) thin-film transistors (TFTs) with organic channels have been investigated with a ferroelectric gate material, poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] [1][2][3][4][5][6] under the basic principles from conventional Si-based ferroelectric field-effect transistors (FeFET), preparing the advent of transparent or flexible device technologies on glass and plastic substrates. Beta-phase crystalline P(VDF-TrFE) films generally have an induced remnant polarization of %10 mC cm À2 if polarized over their coercive electric field (E-field), formed through spin casting and subsequent optimum curing processes. [2,4,7] Researchers presented decent NVM properties of polymer channel NVM-TFT with P(VDF-TrFE) in their recent works: low leakage, relatively low switching voltage, [2] and a quite high switching speed. [1,2,6] They also reported the physical properties of the unit ferroelectric polymer layer. [8][9][10][11][12][13][14][15] Nonetheless, a challenging problem remains to be overcome prior to any practical application of this ferroelectric polymer towards NVM-TFT on flexible plastic or glass substrates: it is the inferior field mobility (less than %10 À2 cm 2 V À1 s À1) of present polymer-based NVM-TFTs, which is due to the intrinsic low channel mobility of polymer-based semiconductors and also due to the rough surface of spin-cast P(VDF-TrFE) layers. Moreover, obtaining low leakage current from spin-cast crystalline ferroelectric polymer films may require quite sensitive care [2] in the solvent selection and in the coating processes of purified polymers. Our previous report shows some high mobility (0.36 cm 2 V À1 s À1 ) ZnO-based NVM-TFTs with poly-4-vinylphenol (PVP)/P(VDF-TrFE) double layers, where the PVP overlayer suppressed current leakage of P(VDF-TrFE) but also caused poor retention, inducing depolarization electric field in the ferroelectric P(VDF-TrFE) layers.[16] Here, we adopt a single P(VDF-TrFE) layer of short-range-order crystalline phase as the nonvolatile memory component for a reproducible lowcurrent-leakage ferroelectric, to be applied onto high-mobility p-channel pentacene channels on flexible plastic substrates and also onto high-mobility n-channel ZnO channels on glass. Our limited-crystalline ferroelectric layer still showed good remnant polarization of maximum %7 mC cm À2, and the pentacene-and ZnO-based NVM-TFTs with such short-range-order crystalline P(VDF-TrFE) layer reproducibly demonstrated maximum field mobilities of 0.1 and 1 cm 2 V À1 s À1 , respectively, with low leakage current densities of a few nanoamperes (%1 Â 10 À6 A cm À2 ), low switching voltages of %20 V for write/erase (in 50 ms pulse), low operation (after switching) voltages of %5 V, and long retention of over 10000 s. In particular, our ZnO-based NVM-TFTs displayed a large memory window of 20 V, which is the maximum obtainable from 200 nm-thick P(VDF-TrFE).Device cross-sections in Figure 1a display our pentacene-and ZnO-based NVM TFTs with the short-range-order crystalline P(VDF-TrFE)...

We report on the fabrication of pentacene-based nonvolatile memory thin-film transistors (NVM-TFTs) with thin poly(vinylidene fluoride/trifluoroethylene) ferroelectric gate insulators. Our NVM-TFT adopts flexible polyethersulfone substrate and operates under the low voltage write-erase (WR-ER) pulses of ±13∼±20 V with field effect mobilities of 0.1–0.18 cm2/V s, depending on the ferroelectric polymer thickness. Our NVM-TFT displays good memory window (ΔV) of 2.5–8 V and also exhibits WR-ER current ratio of 20–40. The retention properties persist over ∼10 000 s and the dynamic response for WR-ER pulses demonstrates clear distinction of WR-ER states under the short switching pulse of 50 ms.

We report on the fabrication of ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with thin poly(vinylidene fluoride/trifluoroethylene) [P(VDF-TrFE)] ferroelectric layer. Our NVM-TFT operates on glass substrates under low voltage write-erase (WR-ER) pulse of ±20 V with a maximum field effect mobility of ∼1 cm2/V s, maximum memory window of ∼20 V, and WR-ER current ratio of 4×102. When the NVM-TFT has a modified channel/ferroelectric interface with an inserted thin Al2O3 buffer layer, our device shows long retention time of more than 104 s, which is much enhanced compared to that of the other device without the buffer. The dynamic response of our devices with or without the buffer was clear enough to distinguish the WR and ER states as performed with 300 ms pulse.

We report on the fabrication of N,N'-ditridecyl-perylene-3,4:9,10-tetracarboxylic diimide-C13 (PTCDI-C13), n-channel organic thin-film transistors (OTFTs) with 30 nm Al(2)O(3) whose surface has been un-modified or modified with hexamethyldisilazane (HMDS) and thin hydrophobic CYTOP. Among all the devices, the OTFTs with CYTOP-modified dielectrics exhibit the most superior device performance and stability. The optimum post-annealing temperature for organic n-channels on CYTOP was also found to be as low as 80 °C, although the post-annealing was previously implemented at 120-140 °C for PTCDI domain growth in general. The low temperature of 80 °C hardly damages the CYTOP/n-channel organic interface which is deformed at a temperature higher than the glass transition temperature of CYTOP (∼110 °C). The pentacenequinone passivation layer turned out to be helpful to keep the interfacial trap density minimum, according to the photo-excited charge collection spectroscopy results for our 80 °C-annealed OTFTs with CYTOP-modified dielectrics.

We report on the fabrication of ZnO-based depletion-load-type inverter composed of two n-channel ZnO thin-film transistors (TFTs) with a low-k poly-4-vinylphenol and high-k poly(vinylidene fluoride-trifluoroethylene) double polymer dielectric. One of the two ZnO channels in the inverter was illuminated by 352 nm wavelength ultraviolet so that the illuminated ZnO channel might be depleted. That ZnO-TFT plays as a driver transistor in the inverter set where the original TFT is used as a load one. The both TFTs show the same mobility of ∼0.3 cm2/V s and our inverter operates with a voltage gain of ∼4 at low supplied voltages (5–7 V), demonstrating a dynamic response of ∼20 ms.