As Moore predicted in 1965, the scale of microelectronic devices continues to diminish at tremendous speed, and today the limitations of conventional 2D scaling make such 3D applications as TSV (through-silicon via) and high-stacked thin-die packaging technologies extremely attractive. However, their complicated structures and thermal-cycled processes generate enormous interfacial stresses. In particular, TSV-to-CPB (copper pillar bump)-stacked structures manufactured under various processing conditions have serious stress-induced reliability problems: stresses can be high enough to cause delaminated or open-crack failures. Many technologies have been developed for measuring residual stress, but destructive techniques such as the holedrilling and cutting methods are too bulky to use at microscales and non-destructive techniques such as XRD (Xray diffraction), BN (Barkhausen noise) and the curvature method using the Stoney equation yield averaged results that are inappropriate in the local assessment of TSV and CPB interfaces. NIT (nanoinstrumented indentation testing), on the other hand, offers many advantages since it can give a micropartial characterization of stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure the micropartial residual stress between CPB and TSV through nanoinstrumented indentation testing. To verify our measured outputs, we observe cross-sectioned microstructure of TSV and CPB using an ion miller and ion-beam image by FIB (focused ion beam), and discuss the textures of variously structured and processed TSV and CPB interfaces. In addition, we used finite element analysis (ABSYS) to simulate the stress distribution around them. Our study will, we hope, be useful in reliability-based quantitative design by defining keep-out zones between TSVs.Keywords: TSV (through silicon via); Micropartial residual stress; NIT (nanoinstrumented indentation testing); Grain growth model; 3DI (3-dimensional integration). IntroductionAs conventional 2D scaling of microelectronic devices has severe limitations, 3D chip stacking is clearly attractive for high performance at low cost in applications such as CMOS image sensors (CIS), stacked memories, highperformance processor-memory assemblies and advanced system-in-package (SiP) leading to heterogeneous integration.

Many studies have characterized the residual stress around TSV by using direct experimental measurement, finite element simulation, and microstructural analysis. The experimental approach is very useful in its speed and direct compatibility with processing, but cannot be used under all circumstances. Instrumented indentation testing, on the other hand, has many advantages: easy sample preparation and simple algorithms lead to a simple characterization of the micropartial stress between samples with the load difference at the same indentation depth. However, the current indentation method has the weak point that we cannot measure the residual stress when the stress-free state does not exist. Here we suggest a new algorithm to measure residual stress without knowledge of the stress-free state by analyzing the plastic pile-up mechanism around the contact area due to residual stress and using the invariant indentation properties obtained from the stressed state. We introduced this new algorithm into TSV-stress analysis to obtain the KOZ (keep out zone). In addition, we used in-situ SEM (scanning electron microscope) indentation to characterize more accurately the KOZ in the silicon around TSV, even in very minute areas.