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The massive parallelism and interconnectivity possible with optoelectronic systems requires the development of fast optoelectronic array processors. The arrays must be fast, with frame rates greater than 20 MHz, in order to effectively compete with electronics. The arrays must also have a large number of pixels (> 104) and perform a logic or memory function. We have designed, fabricated and are in the process of testing an array that can meet these system requirements. This paper discusses our array design and presents some preliminary data.

The design and fabrication of optoelectronic arrays poses a new set of problems not encountered with individual devices. These include smaller feature size, tighter tolerances, a bus structure, planarization and step coverage issues. The later two issues are particularly problematic with vertically integrated devices, such as the LAOS, since the mesas are greater than 3 μm high. This paper discusses these design/fabrication issues and illustrates some solutions.

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