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Deposition of undoped and in situ boron-doped polycrystalline silicon-germanium (poly-Si1−xGex) films on oxide has been investigated at temperatures below 625 °C and a pressure of 4 Torr in a rapid thermal chemical vapor deposition system. The influences of reactant gases such as Si2H6, SiH4, GeH4, and B2H6 on the nucleation behavior, and structural properties of poly-Si1−xGex films formed on oxide were studied. The experimental results showed that in situ boron-doped or undoped poly-Si1−xGex films can be directly deposited on oxide without an initial Si predeposition layer to provide the necessary nucleation sites on the surface when using Si2H6 as the Si source gas. However, when SiH4 was used as the Si source gas, only in situ boron-doped films can be deposited nonselectively on the oxide without the initial Si predeposition layer, and to deposit undoped poly-Si1−xGex films, Si predeposition is needed, otherwise Si1−xGex islands are formed on the oxide. X-ray diffraction analysis showed that poly-Si1−xGex films deposited using Si2H6, GeH4, and B2H6 gas mixture have three singular peaks corresponding to {311}, {220}, and {111} planes, thus indicating the Si1−xGex alloy is formed. In addition, we found that B2H6 gas has a minor effect on the Ge incorporation into the films but reduces the overall deposition rate.

The influence of gate dopant concentration and thermal budget on the reliability of tunnel dielectric films was studied. Metal oxide semiconductor (MOS) capacitors were furnace annealed after gate formation, floating gate devices were fabricated with interpoly dielectric films either grown by furnace oxidation or deposited by rapid thermal chemical vapor deposition (RTCVD); the latter process is associated with a much lower thermal budget. Ion implanted amorphous silicon was employed for the gate electrodes of the MOS capacitors and for the floating gate layers of the memory devices. The reliability of the dielectrics was evaluated under a constant current stress, and the cycling endurance of the floating gate devices was examined. It was found that tap generation and charge trapping increase with increasing annealing time and increasing dopant concentration, while charge to breakdown (Q84) decreases with increasing annealing time. The cycling endurance plot for the floating gate devices revealed little distortion of the threshold voltage window for devices with the low thermal budget RTCVD interpoly dielectric film. Based on this study, a low thermal budget process is preferable for the formation of the interpoly dielectric.

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The quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.