Impact of Floating Gate Dopant Concentration and Interpoly Dielectric Processing on Tunnel Dielectric Reliability

Abstract

The influence of gate dopant concentration and thermal budget on the reliability of tunnel dielectric films was studied. Metal oxide semiconductor (MOS) capacitors were furnace annealed after gate formation, floating gate devices were fabricated with interpoly dielectric films either grown by furnace oxidation or deposited by rapid thermal chemical vapor deposition (RTCVD); the latter process is associated with a much lower thermal budget. Ion implanted amorphous silicon was employed for the gate electrodes of the MOS capacitors and for the floating gate layers of the memory devices. The reliability of the dielectrics was evaluated under a constant current stress, and the cycling endurance of the floating gate devices was examined. It was found that tap generation and charge trapping increase with increasing annealing time and increasing dopant concentration, while charge to breakdown (Q84) decreases with increasing annealing time. The cycling endurance plot for the floating gate devices revealed little distortion of the threshold voltage window for devices with the low thermal budget RTCVD interpoly dielectric film. Based on this study, a low thermal budget process is preferable for the formation of the interpoly dielectric.