By using transmission line measurements of arbitrary characteristic impedance, this paper introduces an alternative method to de-embed parasitic structures such as pads and interconnection lines. The proposed method uses two uniform transmission lines of arbitrary characteristic impedance as calibration standard (L-L method). The two transmission lines have the same characteristic impedance, but different lengths. Experimental S-parameters data of on-wafer CMOS FETs de-embedded with the proposed L-L method, Mangan and the Pad-Open-Short De-embedded (PSOD) methods are compared. The S-parameter data deembedded with both methods the PSOD and the proposed two-tier L-L show high correlation. Therefore the proposed method is validated.

This article presents a method to extract the elements of the electrical equivalent circuit model CMOS pads using two uniform transmission lines fabricated on a lossy Si substrate. The lengths of the uniform transmission lines are different, while its characteristic impedances are equal and can be of an arbitrary value. The proposed method is useful for modeling CMOS pads that can be represented by symmetrical and reciprocal ABCD matrices, denoted as [Mpad]. Then a T‐network is used to represent the CMOS pad and its elements are determined converting [Mpad] into a Z‐parameters matrix. Experimental data from 0.4–20 GHz show a high correlation with theoretical data. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:3033–3037, 2013

No abstract

The proposed architecture is based on the linear response f 0 vs. T of a Voltage Controlled Oscillator (VCO), which is used as a temperature sensor. The simplicity of the architecture makes digital integration in a CMOS technology 0.5um, 5V, N-Well feasible; this is achieved by using basic combinational and sequential digital circuit to implement the characteristic equation for the temperature depending on the oscillation frequency.

This paper deals with modeling of drain current IDS(VGS,VDS) and intrinsic nonlinear capacitances Cgs(VGS,VDS) and Cgd(VGS,VDS) of the CMOS FET by means of empirical analytical expressions. The proposed models are based on exponential series allowing modeling of the CMOS FET from the linear to the breakdown region. Several High Voltage CMOS (HVMOS) FETs were used to validate the proposed models under pulsed DC, small and large signals. The high correlation between simulated and measured data supports the capability of the proposed empirical model to predict the electrical behavior of the CMOS FET. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:563–567, 2017