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The detection of early failures in electromigration (EM) and the complicated statistical nature of this important reliability phenomenon have been difficult issues to treat in the past. A satisfactory experimental approach for the detection and the statistical analysis of early failures has not yet been established. This is mainly due to the rare occurrence of early failures and difficulties in testing of large sample populations. Furthermore, experimental data on the EM behavior as a function of varying number of failure links are scarce. In this study, a technique utilizing large interconnect arrays in conjunction with the well-known Wheatstone Bridge is presented. Three types of structures with a varying number of Ti/TiN/Al(Cu)/TiN-based interconnects were used, starting from a small unit of five lines in parallel. A serial arrangement of this unit enabled testing of interconnect arrays encompassing 480 possible failure links. In addition, a Wheatstone Bridge-type wiring using four large arrays in each device enabled simultaneous testing of 1920 interconnects. In conjunction with a statistical deconvolution to the single interconnect level, the results indicate that the electromigration failure mechanism studied here follows perfect lognormal behavior down to the four sigma level. The statistical deconvolution procedure is described in detail. Over a temperature range from 155 to 200 °C, a total of more than 75 000 interconnects were tested. None of the samples have shown an indication of early, or alternate, failure mechanisms. The activation energy of the EM mechanism studied here, namely the Cu incubation time, was determined to be Q=1.08±0.05 eV. We surmise that interface diffusion of Cu along the Al(Cu) sidewalls and along the top and bottom refractory layers, coupled with grain boundary diffusion within the interconnects, constitutes the Cu incubation mechanism.

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10nm fin width have been demonstrated.A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension. IntroductionFinFETs are promising candidates for sub-20nm scale CMOS devices because of their excellent scalability [1-8]. Primary challenges for FinFETs are the formation of uniform and narrow fins and the reduction of S/D series resistance. The sidewall transfer (SWT) process was proposed to form sub-lithographic fins and reduce the line edge roughness of the fins (Fig.1) [1]. However, the integration technology for the application of SWT process to both fin and gate formation has not been reported yet. On the other hand, it is necessary to deposit silicon selectively on the narrow fins for the reduction of the series resistance by increasing the fin width in S/D regions. However, this process has been very difficult because of the residue of gate sidewall spacer material left on the fin sidewall and the agglomeration of narrow fins.In this paper, we report the FinFET process integration technology including improved SWT process applied to both fins and gates. We also present the device characteristics of the ultra-small FinFET with 15nm gate length and 10nm fin width. A new process technique for the selective gate sidewall spacer formation is also proposed and the advantages of this new approach are experimentally demonstrated.

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