Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

Okano, K.; Izumida, T.; Kawasaki, H.; Kaneko, A.; Yagishita, Akira; Kondo, Takahisa; Kondo, Masaki; Ito, S.; Aoki, Naofumi; Miyano, K.; Ono, Tetsuo; Yahashi, K.; Iwade, K.; Kubota, T.; Matsushita, T.; Mizushima, Ichiro; Inaba, S.; Ishimaru, K.; Suguro, K.; Eguchi, Kazuhiro; Tsunashima, Y.; Ishiuchi, H.

doi:10.1109/iedm.2005.1609454

Cited by 60 publications

(27 citation statements)

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“…The proposed device exhibits a much better short-channel behavior as compared with the standard FinFET structure, and, hence, it is better scalable for channel lengths below 20 nm. The proposed device can be fabricated by using a standard siliconon-insulator (SOI) FinFET process along with an extra antipunchthrough implant similar to the one used for a bulk FinFET [8] device. The BS FinFET can also be fabricated in a standard bulk FinFET process without an extra mask.…”

Section: Introductionmentioning

confidence: 99%

“…Bulk FinFETs are found to have less defect density and process complexity along with several other advantages such as better heat dissipation capability and lower cost [7]. Bulk FinFETs can be fabricated with an extra implant to increase the doping in the inactive fin region to suppress the source-to-drain coupling through the substrate [8]. Although the FinFET devices show excellent promise, they still suffer from issues such as process complexity, additional parasitic capacitances due to the nonplanar nature of the structure, and width quantization effects.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Shrivastava

Baghini

Sharma

et al. 2010

IEEE Trans. Electron Devices

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Abstract-For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, powerdelay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.Index Terms-Bulk fin-shaped field-effect transistor (FinFET), electrothermal, fin-shaped field-effect transistor (FinFET), selfheating, short-channel performance, spacer, width quantization.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Shrivastava

Baghini

Sharma

et al. 2010

IEEE Trans. Electron Devices

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“…Also, we can see that the doping profiles (ii) and (iii) give better I OFF when compared to the conventional doping profiles. Note that in both the cases, the heavier doping in the lower fin region is lower compared to what has been reported [6]. As has been shown, the conventional profiles give rise to a higher I OFF value due to the band-to-band-tunneling (BTBT) currents owing to their heavier doping concentrations.…”

Section: DC Device Simulationsmentioning

confidence: 65%

“…We use the term "upper fin" to represent the fin region which is actually controlled by the gate and "lower fin" to represent the fin region which is covered by the T ins . The proposed bulk FinFET structures [6]- [8] use a heavily doped upper fin/channel doping and a heavier lower fin doping to control the short-channel effects (SCEs). This corresponds to the profile case (i) as shown in Fig.…”

Section: DC Device Simulationsmentioning

confidence: 99%

Device Design and Optimization Considerations for Bulk FinFETs

Manoj

Nagpal

Varghese

et al. 2008

IEEE Trans. Electron Devices

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Abstract-Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.

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“…So, it is important to optimize bulk FinFET performance as in SOI FinFET. The earlier bulk FinFET structures [11,12,13] use a heavily doped upper Fin/channel doping and a heavier lower fin doping to control the short-channel effects (SCEs) but this results in a channel mobility degradation causing a lower ION/IOFF ratio. Therefore different Bulk structures are studied can compared for non uniform doping profiles.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Pie-gate Bulk FinFET Structure

Tripathi¹,

Vadthiya²,

Mishra³

2012

IJCA

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In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET. General termsBulk Fin-shaped field-effect transistor (FinFET), shortchannel performance, SS, DIBL, sentaurus TCAD device simulator.

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Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

Cited by 60 publications

References 0 publications

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Device Design and Optimization Considerations for Bulk FinFETs

Optimization of Pie-gate Bulk FinFET Structure

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