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High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high density 3D LSIs such as (i) thermo-mechanical stress exerted by W TSVs used for signal lines and Cu TSVs used for power/ground lines in active Si, (ii) external gettering (EG) role played by sub-surface defects in thinned Si substrate, and (iii) effect of local stress induced by P-bumps on device characteristics are discussed. By annealing at the temperature of 300 , both Cu (via size 10Pm) and W (via size 1Pm) square TSVs induce only compressive stress at small TSV spacing which will seriously affect the mobility in active Si area, and thus device characteristics. Large compressive stress not only leads to extrusion and peeling of TSV metal, but also die cracking, and it will adversely impact on the reliability of 3D-LSIs. Then it was proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI. Sub-surface defects at dry polished (DP) surface well act as potential EG sites for Cu contamination. Influences of mechanical stress induced by P-bumps on device characteristics were also evaluated and ultra-small size In-Au P-bump technology has been developed to minimize the influences of P-bumps on device characteristics. Introduction 3D integration is an enabling technology to realize high-performance and low-cost system on chip by vertically stacking several functional dies that are interconnected by embedded TSVs and P-bumps. Although Cu is widely used for interconnects [1] due to its lower resistance and improved electro migration properties, meticulous care is required not only to keep the contamination risks minimized [2], but also it is difficult to fill sub-micron via (I=0.6~1Pm). High end 3D-LSI die requires more than 10 4 to 10 5 P-bumps and TSVs per chip and the die thickness of <10 Pm with nearly zero remnant stress [3]. Going by this, W TSVs may outperform Cu TSVs not only due to its ability to form sub-micron vias, but also (i) W is not a potent diffusant in Si substrate as Cu and (ii) it only leaves very minimum stress in active Si owing to smaller difference in co-efficient of thermal expansion (CTE) between W and Si. Therefore W-TSV is preferable for high density and high speed TSVs with small diameter and small capacitance for signal lines. However, W-TSV is not suitable for power/ground (GND) lines because of its higher resistance. Cu-TSV with larger diameter and lower resistance should be employed for TSVs for power/GND lines. Cu-TSVs with larger diameter are more preferable to suppress Cu diffusion since a barrier metal such as Ta can be conformally and uniformly formed into deep trench for TSV which effectively suppresses Cu diffusion. We can also suppress the influences of Cu diffusion on device characteristics by placing Cu-TSVs for power/GND lines apart from the active areas. Thus, we have proposed a high density 3D-LSI using W/Cu hybrid TSVs as shown in Fig. 1 and 2. The Si ...

In general, metal diffusion bonding is carried out at a temperature in the range of 300 ∼ 400 °C and is well documented [1]. However, the knowledge of metal bonding at low temperatures below 300 °C is inadequate yet. On the other hand, low temperature metal bonding is of importance in realizing advanced integrated devices such as MEMS-Semiconductors and high-brightness LED. This paper reports the results of a feasibility study of low-temperature metal bonding with the use of Au-Au diffusion bonding technique.

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