Currents owing in the power and ground P&G buses of CMOS digital circuits a ect both circuit reliability and performance by causing excessive v oltage drops. Excessive v oltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point i n the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the speci c input patterns that are applied to the circuit. Since it is prohibitively expensive t o e n umerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a patternindependent, linear time algorithm iMax that estimates at every contact point, an upper bound envelope of all possible current w a v eforms that result by the application of di erent input patterns to the circuit. The algorithm is extremely e cient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a n o v el partial input enumeration PIE technique to resolve signal correlations and signi cantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-o and are applicable to VLSI circuits.

Excessive power supply and ground currents in integrated circuits can severely a ect circuit reliability and performance. Some of the problems arising from excessive current ow are : 1 excessive voltage drop glitches on the power ground lines, which can lead to soft errors, and 2 large instantaneous power dissipation, which causes overheating and ultimately leads to performance d e gradation. Maximum current estimates are, therefore, needed i n the supply lines in order to determine the severity of these problems. These currents, however, depend on the speci c input patterns that are applied to the circuit. Most previous work in this area has focused o n search techniques that attempt to locate the worst case current by searching for the corresponding worst case input patterns. However, since the input space is huge, search-based algorithm for this problem can take an exponential amount of time, in the worst case. In this paper, we propose a pattern-independent, linear-time algorithm that estimates an upper bound for the Maximum Envelope Current MEC waveform. The MEC waveform is a point-wise maximum on all the possible waveforms that the circuit can draw. Experimental results on several benchmark circuits are p r ovided t o establish the usefulness of this approach.

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Timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing and capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude.