No abstract

No abstract

Fluctuations in manufactured integrated circuit parameters may dramatically reduce the parametric yield. Yield maximization can be formulated as an unconstrained optimization problem in nominal parameter values, which is known as design centering. The high expense of yield evaluations, the absence of any gradient information, and the presence of some numerical noise obstruct the use of the traditional derivative-based optimization methods. In this article, a novel design centering algorithm is presented, which consists of a non-derivative unconstrained optimizer coupled with a variance reduction estimator. The used optimizer combines a trust region mechanism with quadratic interpolation and provides efficient use of yield evaluations. The stratified sampling technique is used to develop a lower variance yield estimator that reduces the number of circuit simulations required to reach a desired accuracy level. Numerical and practical circuit examples are used to demonstrate the efficiency of the proposed algorithm with respect to other methods in the same field.

No abstract

Absrmer-This paper presents a new approach to optimal design centering, the optimal assignment of paramete-r tolerances and the determination and optimization of production yield. Based upon muftidimensionaf linear cuts of the tolerance orthotope and uniform distributions of outcomes between tolerance extremes in the orthotope, exact formulas for yield and yield sensitivities, witb respect to design parameters, are derived.'Ibe formulas employ tbe intersections of the cuts with the orthotope edges, the cuts themselves being function.9 of the original design constraints. Our computatfonal approa& involves the approximation of all the constraints by low-order multidimensional polyuomiak. 'f&se approximations are continually updated during optimization. fnberent advantages of the ap proximatious which we have exploited are that explicit sensitivities Of the design performance .&e not required, available simulation progranrs can be used, inexpensive function and gradient evaluations cau be made, hexpensive calculations at vertices of the tolerance orthotope are facilitated during optimization and, subsequently, inexpensive Monte Carlo verification is possible. Sile circuit examples illustrate worst case design and design with yields of less then 100 percent. Ihe examples also provide verification of the formulas and algorithms.