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This paper presents an evaluation of multiple-valued packet multiplexing scheme for a Network-on-Chip (NoC) architecture. In the NoC architecture, data is transferred from one Processing Element (PE) to another PE through the routers in the form of a packet. A router, suitable for both the binary and the multiple-valued packets, is constructed using the Multiple Valued Source-Coupled Logic circuits. A packet is composed of flag, destination PE address and data fields. In the NoC architecture, packets are generated by microprogram control. In the proposed scheme, two binary packets are multiplexed if the destination PE addresses are the same. Based on address matching, packets are transferred from a source PE to a destination PE autonomously. As a result, the total number of packets can be reduced. The router is designed using 0.18μm CMOS design rule. HSPICE simulation results show that the delay of the router is significantly small for high speed packet transfer. Reduction of microprogram control storage is remarkable in the proposed scheme, because the data transfer can be done autonomously. The advantage is evaluated by simple analysis, and comparison with a conventional pipelined bus architecture is done.

This paper presents a fine-grain cell design for a Multiple-Valued (MV) reconfigurable VLSI using a single Differential-Pair Circuit (DPC). The VLSI involves a bitserial localized data transfer architecture. The cell consists of a Multiple-Valued Source-Coupled Logic (MVSCL)-based threshold logic gate, a dynamic latch and a switch block. The threshold logic gate consists of only one universal comparator. A single DPC is used as a component of the universal comparator. By using programmable current sources for the DPC, the driving capability of the cell and the weight of the output can be changed according to the reconfigured information. The DPC compares a multiplevalued (MV) input with a threshold which is provided by a programmable threshold voltage generator. This leads to the high utilization of the cell because almost all the universal comparators in the VLSI chip can be utilized effectively without idle states. Furthermore, fine-grain pipelining increases the throughput of the VLSI. The VLSI is designed using 0.18μm CMOS standard design rule. HSPICE simulation results show that, the throughput and the power consumption are greatly improved in comparison with the equivalent VLSI reported until now.