The overall veriJication approach used in the design and development of the fill custom 64 bit UltraSPARC microprocessor will be described. A balanced hierarchical approach was critical in validating a design with this level of complexity. The tools, developed internally and externally, which aided the verijication effort will also be described. The environment was flexible enough to support various revisions of major tools. The method developed could easily be applied to derivative and next generation microprocessors.

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The new link layer of DVB-H includes Reed Solomon Forward Error Correction (RSFEC), which provides additional robustness and flexibility in system design. RS-FEC is primarily designed as an Equal Error Protection (EEP) scheme. However, it can be extended in a standard compatible way to also implement Unequal Error Protection (UEP) schemes. In this paper we propose an UEP scheme that uses Redundant Transmission (RT) to spread important data over several DVB-H time slices. Basically, the base layer data is repeated in d consecutive time slices thus giving a coderate of 1/d. The time diversity gained through this Inter-Burst RT scheme is shown to be more effective than other proposed UEP schemes based on RS-FEC. Furthermore, this approach can be implemented in a standard compatible way

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Unequal error protection (UEP) schemes for DVB-H can be realized either by redundant transmission of important Base Layer data (UEP-RT) or by giving higher FEC protection to important Base Layer data (UEP-FEC) as shown in the literature. UEP requires division of total source coding bits into Base Layer bits and Enhancement Layer bits with certain shares.In this paper we present the effect of Base Layer Bits-Share on the performance of the above two UEP schemes. It is shown with simulation results that for small Base Layer Bits-Shares such as 10% or 20% of the total source coding bits, UEP-RT outperforms UEP-FEC. Whereas for large Base Layer Bits-Share such as 30%, UEP-FEC is more effective.