In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driver-assisted functionalities. Consequently, a high-performance computing unit is required to provide the demanded power and process these applications while, in this case, vehicle architecture moves toward a centralized architecture. Simultaneously, appropriate software architecture has to be defined to fulfill the needs of the main computing unit and functional safety requirements. However, the process of configuring and integrating critical applications into a vehicle central computer while meeting safety requirements and optimization objectives is a time-consuming, complicated, and error-prone process. In this paper, we firstly present the evolution of the vehicle architecture, past, present, and future, and its current bottlenecks and future key technologies. Then, challenges of software configuration and mapping for automotive systems are discussed. Accordingly, mapping techniques and optimization objectives for mapping tasks to multi-core processors using design space exploration method are studied. Moreover, the current technologies and frameworks regarding the vehicle architecture synthesis, model analysis with regard to software integration and configuration, and solving the mapping problem for automotive embedded systems are expressed. Finally, we propose four research questions as future works for this field of study.

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Designing the new generation of electronic and electrical architectures, guaranteeing reliable communication is a prerequisite. The fulfillment of this requirement is a challenging undertaking that requires advanced expertise and is time-consuming. This paper presents a novel model-based approach for automating the generation of optimized network architectures in the design phase, supporting homogeneous redundant routings. Our results indicate a linear growth of architecture synthesis time if the number of applications is growing while the number of nodes remains constant. Conversely, increasing the number of nodes results in exponential growth of the architecture synthesis time. We believe that the proposed approach contributes to facilitating the design of safe E/E architectures.

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