ABSTRACT

Metallic contaminants on a wafer surface have been known to be a major source of performance failure in IC devices by increasing the p-n junction leakage, degradation of the oxide breakdown voltage and deteriorating the carrier lifetime. 1 With shrinking device geometries, the tolerance level of metallic contaminants is becoming more stringent. It has been reported that metallic contamination on a silicon surface needs to be suppressed to less than 1 × 10 10 atoms/cm 2 to manufacture a 64-Mbit DRAM in order to prevent the above-mentioned failures. 2 According to device development and an estimation of the research organization, this level should be down to 1 × 10 9 atoms/cm 2 in the future. With this tendency, analytical techniques used to measure ultratrace metallic contaminants on a silicon surface have also been developed.One of the most prevalent techniques used for measuring metallic contaminants is VPD-DC (vapor phase decompositiondroplet collection). During the VPD procedure, the wafer is exposed to hydrogen fluoride vapor in a closed container to decompose the surface oxide layer. The decomposition reaction of silicon oxide by hydrogen fluoride vapor is expressed by SiO2 + 6HF ⇔ H2SiF6 + 2H2O.(1)Metallic contaminants remain on the wafer surface after the decomposition of silicon oxide. In the DC procedure, these metallic contaminants are collected into a small amount of ultrahigh-purity liquid droplets by scanning the wafer surface. A liquid droplet prepared by VPD-DC is analyzed by different trace-element analysis techniques, such as atomic absorption spectrometry (VPD-AAS), 3-7 inductively coupled plasma-mass spectrometry (VPD-ICP-MS) 5,8-10 and total reflection X-ray fluorescence (VPD-TXRF). 4,[11][12][13] DC is a procedure used to collect and preconcentrate all impurities into liquid droplets. The composition of the collecting solution as well as the chemistry of the collected contaminants determine the collection efficiency. Morinaga et al. have reported that metallic contaminants deposit on a silicon wafer surface in a wet process depending on the type of metal element, the type of solution and the type of substrate. 14 Therefore, a chemical reaction of metal at the silicon surface during VPD-DC can influence the collection efficiency of a metallic contaminant. However, there have been few reports concerning the collection efficiency of the VPD-DC procedure. In this experiment, the collection efficiency of VPD-DC sample preparation was investigated for 14 elements (Na, Mg, Al, K, Ca, Cr, Fe, Mn, Co, Ni, Cu, Zn, Mo and Ti) on four types of silicon wafers. Standard solutions containing 7 elements in each solution were intentionally contaminated on a silicon wafer surface. The contaminated area was scanned with various collecting solutions in the VPD-DC procedure and a droplet containing metallic contaminants, collected from the silicon wafer surface, was measured by ICP-MS. The collection efficiency was determined as the ratio of the collected metallic concentration to the initial contamination conce...

The effect of the first-step heat treatment temperature on the bulk microdefect (BMD) and oxidation-induced stacking fault (OiSF) formation in two kinds of heavily boron-doped silicon wafers, with and without an OiSF ring area, were investigated by comparing it with that in lightly boron-doped wafers. The BMD density was observed to be higher in the heavily doped silicon than in the lightly doped one at the same oxygen concentration. Unlike in the lightly doron-doped silicon, in the heavily boron-doped silicon, OiSFs were formed over the entire wafer surface regardless of the OiSF ring position when the first-step heat treatment was carried out at 900°C.

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The dielectric breakdown of oxides with various thickness between 5–70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (t OX) and showed a maximum value at the t OX range of 10–20 nm. On the other hand, COP-free wafers showed few breakdowns over all the range of t OX. Furthermore, time dependent dielectric breakdown (TDDB) of the vacancy-rich wafers showed higher extrinsic breakdowns than that of the COP-free wafers in the t OX below 20 nm. For the intrinsic breakdown, two groups showed the same charge-to-breakdown (Q BD) along the strength of injection current over all the range of t OX. Especially, only in case of vacancy-rich wafer, abnormal increase of current, i.e., hump phenomena, was observed in the range of electric field below the Fowler-Nordheim (F-N) tunneling.