Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on-formation of filaments in an amorphous medium-is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

Although flakes of two-dimensional (2D) heterostructures at the micrometer scale can be formed with adhesive-tape exfoliation methods, isolation of 2D flakes into monolayers is extremely time consuming because it is a trial-and-error process. Controlling the number of 2D layers through direct growth also presents difficulty because of the high nucleation barrier on 2D materials. We demonstrate a layer-resolved 2D material splitting technique that permits high-throughput production of multiple monolayers of wafer-scale (5-centimeter diameter) 2D materials by splitting single stacks of thick 2D materials grown on a single wafer. Wafer-scale uniformity of hexagonal boron nitride, tungsten disulfide, tungsten diselenide, molybdenum disulfide, and molybdenum diselenide monolayers was verified by photoluminescence response and by substantial retention of electronic conductivity. We fabricated wafer-scale van der Waals heterostructures, including field-effect transistors, with single-atom thickness resolution.

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The evolution of copper-based interconnects requires the realization of an ultrathin diffusion barrier layer between the Cu interconnect and insulating layers. The present work reports the use of atomically thin layer graphene as a diffusion barrier to Cu metallization. The diffusion barrier performance is investigated by varying the grain size and thickness of the graphene layer; single-layer graphene of average grain size 2 ± 1 μm (denoted small-grain SLG), single-layer graphene of average grain size 10 ± 2 μm (denoted large-grain SLG), and multi-layer graphene (MLG) of thickness 5-10 nm. The thermal stability of these barriers is investigated after annealing Cu/small-grain SLG/Si, Cu/large-grain SLG/Si, and Cu/MLG/Si stacks at different temperatures ranging from 500 to 900 °C. X-ray diffraction, transmission electron microscopy, and time-of-flight secondary ion mass spectroscopy analyses confirm that the small-grain SLG barrier is stable after annealing up to 700 °C and that the large-grain SLG and MLG barriers are stable after annealing at 900 °C for 30 min under a mixed Ar and H2 gas atmosphere. The time-dependent dielectric breakdown (TDDB) test is used to evaluate graphene as a Cu diffusion barrier under real device operating conditions, revealing that both large-grain SLG and MLG have excellent barrier performance, while small-grain SLG fails quickly. Notably, the large-grain SLG acts as a better diffusion barrier than the thicker MLG in the TDDB test, indicating that the grain boundary density of a graphene diffusion barrier is more important than its thickness. The near-zero-thickness SLG serves as a promising Cu diffusion barrier for advanced metallization.