In this paper, we propose a novel hardware architecture for an intra‐prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing 4×4 Hadamard transform and quantization during 16×16 prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix 0.35 µm TLM (triple layer metal) library.

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In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the 4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio ( 28 versus 24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.Index Terms-Doherty power amplifier, inverted Doherty power amplifier (IDPA), load modulation, offset line, 4 differential quadrature phase-shift keying (DQPSK).

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