An intra-panel interface system employing data scrambling for EMI suppression is presented in this work. The proposed data scrambler targets two sources of EMI found in a periodic clockembedded interface system: active data field and horizontal blanking period (HBP). For verification, an intra-panel interface based on enhanced Reduced Voltage Differential Signaling (eRVDS) with data scrambling function is implemented in CMOS technology, and EMI measurement of the prototype shows that suppression of data-induced EMI can be successfully achieved by the proposed scrambling technique.

-An intra-panel interface addressing all of the high-speed, low-power, and lowelectromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4-Gbps data-rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power-saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin-film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65-nm and 180-nm complementary metal-oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band-20 and GSM 850 bands. The proposed power-saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced-voltage differential signaling interface circuit.

No abstract

This paper presents a 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers. To reduce size overhead from the dual‐mode interfaces, we propose the termination circuit that shares 50‐Ω terminations and common‐mode capacitors while maintaining a perfectly matched load balance. The proposed dual‐mode receiver can support 14‐Gb/s total bandwidth in each interface mode, resulting in broad compatibility with application processors. A mobile display driver using the proposed dual‐mode receiver is fabricated in a 28‐nm high‐voltage CMOS process and verified up to 3.5 Gb/s per lane in the D‐PHY mode and 2.2 Gs/s per trio in the C‐PHY.

This paper presents a 14-Gb/s dual mode receiver with MIPI D-PHY and C-PHY interfaces for mobile display drivers. To reduce size overhead from the dual mode interfaces, we propose the termination circuit that can share 50-Ω terminations and common-mode capacitors while maintaining a perfectly matched load balance. The proposed dual mode receiver supports up to 14 Gb/s total bandwidth in each interface mode, resulting in broad compatibility with application processors. A mobile display driver using the proposed dual mode receiver is fabricated in a 28-nm high-voltage CMOS process and verified up to 3.5 Gb/s per lane in the D-PHY mode and 2.2-Gs/s per lane in the C-PHY.