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This paper describes a circuit theoretic formulation for simulating the Schrödinger equation using classical analog circuits. Update equations for a finite difference time domain (FDTD) Schrödinger equation solver with absorbing boundary conditions (ABCs) are used to derive signal flow graphs that naturally map to switched capacitor (SC) circuits. A prototype implementation of a fully-parallel SC FDTD solver with 128 spatial points and a clock frequency of 2 MHz is analyzed and simulated using a standard 180 nm CMOS process.

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