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CONVENTIONAL DRAMs ARE DESIGNED PRIMARILY for low cost, and their performance has been improving only gradually with each successive generation. This paper will describe a 128Kx 4 DRAM designed for high speed while retaining the traditional density advantage of the 1-transistor DRAM cell. Waveforms in Figure 1 show a row access of 20ns, measured at 5.0V, 25OC, and 50pF load, and column access of 7.5ns under the same conditions. In Figure 2, the high-speed page mode with 12ns cycle into 60pF is shown. The resulting data rate is 330MHz with a page depth of 25633.The chip is 78mm2 and was fabricated in a single-poly, double-metal N-well epitaxial CMOS process with an average feature size of 1.3p.m. Chip features are summarized in Table 1.The large cell size results from the single-poly technology. The cell is about twice the area of a conventional double-poly cell, and the chip is about the same area as a 1Mb design with the conventional cell.into eight 64Kb islands. To reduce power and noise, the chip was quarter selected during each access. Conventional DRAM modes of K S and CAS enable and multiplexed row and column addresses are aupported. Thechip can also beoperated like a pseudo-SRAM by holding CAS low and using RAS as the chip enable clock. The high peak currents require second-layer metal for power distribution, which it also used to strap the polysilicon word lines every 32b t o reduce wordline delay. Power buses are wide metal-2 VDD lines over metal-1 ground lines in a low-inductance transmission-line like structure, and are wired on two sides of the chip to provide short interconnections to circuits. Circuits having large di/dt and peak currents are placed closer t o either chip or island center t o reduce noise and RC delays. Interdigitated layout is used for the large driver devices.The array consists of P-channel folded bit-line cells with 33fF diffusion-storage capacitors. Locating the array in the Nwell decouples the noise from peripheral circuits and decreases SER. Array N-wells are biased t o 1 V above VDD to reduce minority-carrier injection and bitline capacitance and raising the access device threshold. The PMOS devices in peripheral circuits have only VDD N-well bias, yielding a less negative threshold, resulting in faster speed. A substrate bias of -2.5V, generated on-chip, also enhances circuit speed by relaxing constraints on voltage undershoot and latch-up, reducing junction capacitance, and reducing V+ modulation. The cell Figure 3 shows a chip photograph. The cell array is partitioned 'Lu. N., Chao, H., "Half-VDD Bitline Sensing Scheme in CMOS DRAMs", IEEE J. Soiid~State Circuits, p. 451-454; 1984.capacitor has its plate grounded. The work function difference between the N t poly plate and the P-type diffusion storage help in reducing the voltage stress across the storage insulator. Circuit improvements have also been made to enhance both speed and S/N. A boosted wordline circuit serves to accelerate speed and reduce voltage stress on diffused junctions; Figure 4.For a selected wordline, t...

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