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A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/ contact etch ͑VCE͒ processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabricationdefined thresholds of acceptable variations in critical dimension ͑CD͒ of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel VCE electronic design automation tool for design-aware process optimization in addition to the "standard" process-aware design optimization. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J. Micro/Nanolith. MEMS MOEMS Oct-Dec 2009/Vol. 8͑4͒ 043007-2 Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J. Micro/Nanolith. MEMS MOEMS Oct-Dec 2009/Vol. 8͑4͒ 043007-3 Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J. Micro/Nanolith. MEMS MOEMS Oct-Dec 2009/Vol. 8͑4͒ 043007-11 Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J.

A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable of detecting and reporting etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the "standard" process aware design optimization.

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through-silicon-via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation-based design verification flow capable to analyze a design of 3D IC stacks and to determine across-die outof-spec variations in device electrical characteristics caused by the layout and through-silicon-via (TSV)/packageinduced mechanical stress. The limited characterization/measurement capabilities for 3D IC stacks and a strict "good die" requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design-for-manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV-based dies, stacks and packages. A set of physics-based compact models for a multi-scale simulation to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. A strategy for generation of a simulation feeding data and respective materials characterization approach are proposed, with the goal to generate a database for multi-scale material parameters of wafer-level and package-level structures. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10nm strain measurements so far.