The gamma-ray blazar 1611+343 was observed with polarization VLBI mode at 5 GHz in February 1999. The total intensity (I) VLBI image of the source shows a core-jet structure. The jet bends eastward at ∼ 3 mas south of the core. Four components have been detected from results of fitting, with apparent speeds estimated at 6.7 ± 0.7, 2.5 ± 0.3, 4.5 ± 0.5 h −1 c for three jet components (taking H 0 = 100 h km s −1 Mpc −1 , q 0 = 0.5). The polarization (P ) VLBI image of 1611+343 displays the polarized configuration in the jet. The mechanism of the curved jet is discussed.

We investigated the effects of post-gate anneal and WN sputtering power on the gate dielectric integrity of W/WN/TaO x N y /SiO 2 /Si metal oxide semiconductor ͑MOS͒ capacitors. The process damage induced by physical vapor deposited metal gates in the high-permittivity ͑k͒ gate dielectric was partially relieved by a post-gate anneal. This is manifested by reduced leakage current, higher wear-out breakdown voltage, reduced charge trapping, and improved interface characteristics such as reduced hysteresis and interface state density (D it ). We observed a noticeable increase of charge trapping and interfacial roughness at the WN/TaO x N y interface with WN power density while the D it level remained similar. Degradation in the reliability characteristics with sputtering power density might be attributed to irrecoverable damage in the TaO x N y film.With shrinking of complementary metal oxide semiconductor ͑CMOS͒ device dimensions to the sub-0.1 m regime, the vertical dimension of SiO 2 is also being scaled down to less than 20 Å in order to obtain the high device performance and to suppress short channel effects. In this regime of SiO 2 thickness, however, the large gate leakage current due to direct tunneling will increase static power consumption and affect circuit operation. 1 Several highpermittivity ͑k͒ dielectrics have been widely studied to prevent the problems caused by the large gate current. 2-5 Especially, direct metal gate on high-k gate dielectric has attracted a lot of attention because of low resistance in narrow gate lines and no gate depletion that allows the metal/high-k gate stack to have smaller capacitance equivalent thickness ͑CET͒. Since some metals have chemical and thermal instability with dielectrics at elevated temperatures, selection of a stable metal gate on the high-k dielectric is a prerequisite for device application. For instance, the TiN/SiO 2 interface is stable up to 850°C, while the WN/SiO 2 interface becomes unstable over 650°C. 6 TiN unfortunately has chemical reaction with Ta 2 O 5 at temperatures higher than 750°C, resulting in an increase of leakage current. 7 WN gate electrode on Ta 2 O 5 shows better thermal stability and lower leakage current. 8 Other issues of direct metal gates are the metal penetration and plasma damage into the SiO 2 when prepared by the physical vapor deposition ͑PVD͒ method. The damage which is more severe for higher energy sputtering 9 leads to the degradation of reliability, interface, and bulk properties of SiO 2 /Si MOS system; 10-12 however, PVD metal gate on the high-k gate dielectric in terms of process-induced damage has not yet been reported.In this study, we report an in-depth study of sputtered W/WN metal gate on the TaO x N y /SiO 2 gate dielectric, i.e., the effects of post-gate anneal and sputtering power density during WN deposition on the reliability of the high-k gate dielectric. ExperimentalFor the evaluation of PVD metal gate on the high-k gate dielectric, W/WN/TaO x N y /SiO 2 /Si metal oxide semiconductor ͑MOS͒ capacitors were ...

Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti(N) process were investigated in terms of gate contact resistance (R c ) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSi x /TiN bilayer during the postdeposition annealing process. The TiSi x reaction between Ti and p+ polycrystalline silicon (poly-Si) effectively prevents the formation of a parasitic dielectric layer, which could lead to low-gate R c . The TiN reaction between Ti and WN minimizes the occurrence of the TiSi x reaction, which effectively reduces p+ polydepletion caused by the out-diffusion of boron during the postdeposition annealing process. Therefore, poly-Si/Ti/WN/W could be a promising tungsten dual polygate stack, which satisfies high-speed requirements in dynamic random-access memory (DRAM) devices.

Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSi x layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si-N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSi x /poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.