Work function and thermal stability of reactive sputtered Ti1−xAlxNy films were investigated for a metal gate electrode using a metal–oxide–semiconductor (MOS) structure. It is found that the work function (ΦM) values of Ti1−xAlxNy are ranged from 4.36 to 5.13 eV with a nitrogen partial flow rate (fN2). The ΦM values of Ti1−xAlxNy films, 4.36 eV for nMOS (n-Ti1−xAlxNy) and 5.10–5.13 eV for pMOS (p-Ti1−xAlxNy), may be applicable to dual metal gate electrodes. Excellent thermal stability up to 1000 °C was obtained on SiO2 as observed by the negligible change of capacitance equivalent thickness and Al 2p core level spectra for p-Ti1−xAlxNy (y∼1.0,fN2=50%), whereas a limited stability was attained in case of n-Ti1−xAlxNy (fN2⩽40%). The p-Ti1−xAlxNy can be a good candidate for pMOS device feasibility because of good thermal stability, while the n-Ti1−xAlxNy may be applicable for nMOS gate electrode in low thermal devices using damascene gate process.

We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO2/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.

We investigated the effects of post-gate anneal and WN sputtering power on the gate dielectric integrity of W/WN/TaO x N y /SiO 2 /Si metal oxide semiconductor ͑MOS͒ capacitors. The process damage induced by physical vapor deposited metal gates in the high-permittivity ͑k͒ gate dielectric was partially relieved by a post-gate anneal. This is manifested by reduced leakage current, higher wear-out breakdown voltage, reduced charge trapping, and improved interface characteristics such as reduced hysteresis and interface state density (D it ). We observed a noticeable increase of charge trapping and interfacial roughness at the WN/TaO x N y interface with WN power density while the D it level remained similar. Degradation in the reliability characteristics with sputtering power density might be attributed to irrecoverable damage in the TaO x N y film.With shrinking of complementary metal oxide semiconductor ͑CMOS͒ device dimensions to the sub-0.1 m regime, the vertical dimension of SiO 2 is also being scaled down to less than 20 Å in order to obtain the high device performance and to suppress short channel effects. In this regime of SiO 2 thickness, however, the large gate leakage current due to direct tunneling will increase static power consumption and affect circuit operation. 1 Several highpermittivity ͑k͒ dielectrics have been widely studied to prevent the problems caused by the large gate current. 2-5 Especially, direct metal gate on high-k gate dielectric has attracted a lot of attention because of low resistance in narrow gate lines and no gate depletion that allows the metal/high-k gate stack to have smaller capacitance equivalent thickness ͑CET͒. Since some metals have chemical and thermal instability with dielectrics at elevated temperatures, selection of a stable metal gate on the high-k dielectric is a prerequisite for device application. For instance, the TiN/SiO 2 interface is stable up to 850°C, while the WN/SiO 2 interface becomes unstable over 650°C. 6 TiN unfortunately has chemical reaction with Ta 2 O 5 at temperatures higher than 750°C, resulting in an increase of leakage current. 7 WN gate electrode on Ta 2 O 5 shows better thermal stability and lower leakage current. 8 Other issues of direct metal gates are the metal penetration and plasma damage into the SiO 2 when prepared by the physical vapor deposition ͑PVD͒ method. The damage which is more severe for higher energy sputtering 9 leads to the degradation of reliability, interface, and bulk properties of SiO 2 /Si MOS system; 10-12 however, PVD metal gate on the high-k gate dielectric in terms of process-induced damage has not yet been reported.In this study, we report an in-depth study of sputtered W/WN metal gate on the TaO x N y /SiO 2 gate dielectric, i.e., the effects of post-gate anneal and sputtering power density during WN deposition on the reliability of the high-k gate dielectric. ExperimentalFor the evaluation of PVD metal gate on the high-k gate dielectric, W/WN/TaO x N y /SiO 2 /Si metal oxide semiconductor ͑MOS͒ capacitors were ...

Articles you may be interested inEffect of annealing on leakage current in Ba 0.5 Sr 0.5 Ti O 3 and Ba 0.96 Ca 0.04 Ti 0.84 Zr 0.16 O 3 thin films with Pt electrodes Appl. Phys. Lett.Properties of reactive-sputtered Ti 1−x Al x N films for complementary metal-oxide-semiconductor silicon storage node electrode diffusion barriersWe report on the characteristics of sputter-deposited Ti 1Ϫx Al x N ͑TiAlN͒ thin films for storage node electrode barriers of Pt/͑BaSr͒TiO 3 ͑BST͒/Pt metal-insulator-metal ͑MIM͒ capacitors with a comparative study of TiN films. The substrate temperature (T s ) was found to be one of the key factors affecting the properties of TiAlN thin films, i.e., the resistivity of TiAlN is ϳ350 ⍀ cm for high T s deposition ͑ϳ450°C͒ and ϳ1100 ⍀ cm for low T s ͑ϳ100°C͒. The lower resistivity of TiAlN films deposited at high T s ͑450°C͒ is attributed to the ͑200͒ texture with larger grain size and smaller oxygen concentration compared to those prepared at low T s . The electrical characteristics of Pt/BST/Pt MIM capacitors on TiAlN were superior to those on the TiN barrier in terms of smaller equivalent oxide thickness (t ox ), lower tangent ␦, and lower leakage current. Better oxidation resistance of TiAlN over TiN appears to be responsible for the better electrical results, especially with the ͑111͒ or ͑200͒ texture. We also discuss a BST bulge and local thinning due to the Pt deformation on TiAlN over an anneal of 600°C in O 2 , resulting in leakage current degradation of the BST MIM capacitor.

We report the effects of the TiN deposition technique on the generation and annihilation of interface traps and oxide trapped charges in W/TiN/SiO 2 ͑2-6 nm͒/Si metal oxide semiconductor ͑MOS͒ system during direct metal gate process. The TiN films were prepared by reactive sputtering using the Ti target or chemical vapor deposition ͑CVD͒ using TiCl 4 and NH 3 . Sputterdeposited TiN not only generated a high level of interface traps ϳ2 ϫ 10 12 eV Ϫ1 cm Ϫ2 from the bandedge to the near midgap of Si, but also introduced oxide trapped charges (Q ot ) of ϳ1 ϫ 10 12 cm Ϫ2 . The damages annealed out for SiO 2 ͑у3 nm͒ to the range of 2 -3 ϫ 10 11 eV Ϫ1 cm Ϫ2 by the post-metal anneal ͑PMA͒ at 800°C in N 2 or at 450°C in forming gas. The interfacial damages for ultrathin SiO 2 ͑ϳ2 nm͒, however, were hardly capable of relieving even after the PMA of 800°C, resulting in an interface trap density (D it ) in the high 10 11 eV Ϫ1 cm Ϫ2 range. The D it level created after CVD-TiN was as low as ϳ3 ϫ 10 11 eV Ϫ1 cm Ϫ2 with negligible Q ot even without PMA, and this level was further reduced to ϳ1 ϫ 10 11 eV Ϫ1 cm Ϫ2 after PMA. We observed a noticeable increase of the capacitance equivalent thickness when prepared with CVD-TiN plausibly due to Cl from the source gas.With scaling complementary metal-oxide-semiconductor ͑CMOS͒ devices to the 100 nm regime, gate depletion and high gate resistance have become a significant problem for polycrystalline-Si ͑poly-Si͒ gate on ultrathin gate oxide. 1-3 The poly-Si gate depletion in conjunction with boron penetration is especially troublesome for p-type poly-Si on thin SiO 2 ͑Ͻ3 nm͒. One approach to overcome these problems is to use a metal gate electrode deposited directly on the gate dielectrics. [2][3][4][5][6][7][8][9][10][11][12][13] A series of advanced researches on direct metal gates were carried out using W, 4 Mo, 5 WN x , 6 TiN x , 2,6-10 and other metals on SiO 2 . 11-13 Buchanan et al. reported W midgap metal gate compatible with ultrathin dielectric ͑ϳ3 nm͒ and demonstrated symmetric flatband voltages for n-and p-type substrate with a barrier height of 3.70 eV. 4 Some interesting results such as generation of interface traps and reliability degradation of MOS devices due to metal penetration and ion damage during the physical vapor deposition ͑PVD͒ process were presented. 4,5,10-12 To anneal the aforementioned defects, the MOS structures gated with direct metals were subjected to a post-metal anneal ͑PMA͒ at high temperatures or in a forming gas anneal ͑FGA͒. 4,5,[10][11][12] Most recently, the feasibility of W/TiN gate stack has been evaluated for conventional 130 nm CMOS technology and beyond. 3,7-10 W/TiN stack is of technological importance because of its midgap work function, low resistivity, and good diffusion barrier properties. 7-9 While PVD-TiN films sputtered at high temperature showed better electrical properties than those prepared at room temperature, 3 PVD-Mo films deposited at room temperature exhibited less metal penetration and damage. 5 Chemical vapor deposition...