No abstract

Dual damascene [1][2][3][4] technique has been widely applied to IC device fabrication in copper interconnect process. For traditional via-first dual damascene application, a fill material is first employed to fill via to protect over-etching and punch-through of the bottom barrier layer during the trench-etch process. Etch-back process is then applied to remove excess overfill thickness and maintain a greater planar topography. To get better CD control, a thin organic BARC is finally coated to reduce reflectivity for trench patterning but not in this study. It is a multi-step and costly dual damascene process. In this study, a new gap-filling BARC [5] material with good via fill and light absorption features was adopted to explore the via-first dual damascene process by skipping etch-back and BARC coating steps. The results show not only the reduction of process cycle time and cost saving but also the CP yield improvement based on data from pilot production of 0.11/0.13 μm logic device.