A low-power 1Kb phase change random access memory (PCRAM) chip is designed. The chip uses 1T1R (one transistor one resistor) structure and titanium nitride (TiN) bottom electrode (BE) for reducing power consumption. Besides, the write property of the chip is improved by employing a ramp down pulse generator. The chip is fabricated in 130nm CMOS standard technology. The test result shows a 56% power reduction based on TiN BE compared with tungsten (W) BE, which predicts a new direction to realize the commercialization of PCRAM.

Design of a novel initialization circuit is presented in this paper. The initialization circuit is used to supply initialization current to the first test of phase change memory chip after delivery. Inhomogeneous crystalline grain sizes appear in phase change materials used in memory cells during manufacturing process. The crystalline phase with low resistance will convert to amorphous phase with high resistance after initialization, which is called RESET the memory cells to 0. Normal RESET operation current is not high enough to RESET great grain, which deteriorates bit yield of phase change memory chip. In comparison, the higher initialization current will increase bit yield observably.

An error correcting method of BCH code applicable to memory is proposed. The reliability and yield of memories can be efficiently improved by error correcting codes. Due to the limited length of data transfer bits in certain interfaces, check bits are not fully used by most BCH codes. The proposed method takes advantage of the nature of BCH codes to make full use of the check bits, so that more errors can be corrected than the original method. The algorithm can be achieved by pure logic circuits in a parallel way with only gate delay, suitable for special timing applications. The improvement of certain BCH code is evaluated by C++ and the hardware implementation is presented by FPGA.