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This paper presents the results obtained from a systematic study on dielectric planarization using a chemical mechanical polishing (CMP) technique. This technique is readily applicable to intermetal and pre-metal dielectric films for advanced CMOS device fabrication. Results indicate that polishing rates vary with different dielectrics; with BPSG having the highest removal rate, while PECVD nitride having the lowest removal rate. Key parameters in determining the polishing rate are down force pressure and platen rotation speed. It is demonstrated that planarization becomes a reality on patterned wafers.

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