This paper presents the results obtained from a systematic study on dielectric planarization using a chemical mechanical polishing (CMP) technique. This technique is readily applicable to intermetal and pre-metal dielectric films for advanced CMOS device fabrication. Results indicate that polishing rates vary with different dielectrics; with BPSG having the highest removal rate, while PECVD nitride having the lowest removal rate. Key parameters in determining the polishing rate are down force pressure and platen rotation speed. It is demonstrated that planarization becomes a reality on patterned wafers.

Polytetrafluoroethylene (PTFE) has been studied as a low dielectric constant material for ULSI. A novel nanoparticle dispersion of PTFE was developed that permits the spin-coat deposition of PTFE with a thickness range of 0.2 to 1.5 μm. These PTFE nanoemulsions are aqueous emulsions containing sub-50 nm size PTFE particles and surfactant that are thermodynamically stable, optically clear, and have low viscosity and surface tension. The films cast from this nanoemulsion are uniform in thickness with a standard deviation of < 2%. From FTIR spectra, significant amounts of C-F bonds (1153 cm−1 and 1211 cm−1) are detected in the films. The index of refraction from ellipsometry measurement is about 1.35 and the dielectric constant measured from high frequency C-V curves is about 1.85. The dielectric strength is about 170 V/ μm. TGA data indicates a weight loss rate of less than 0.25%/hr. at 425 °C. The moisture absorption is less than 0.01%. After sintering, the films are extremely resistant to chemical attack by sulfuric acid, buffered HF, and positive photoresist developer. The etch rate in an oxygen plasma at 30 W is around 200 nm/min. Stud pull tests indicate good adhesion to SiO2, Al, and Cu. Results of thermal, dielectric, chemical, and adhesion tests indicate that these PTFE films have potential for use as an integrated circuit dielectric material.

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