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Multi‐stage all‐pass networks can be used to realise broadband phase shifters with low phase error. In this study, single‐stage and two‐stage all‐pass networks with internal switched capacitors are investigated. Potentials and limitations of using the all‐pass networks with internal switched capacitors for phase shifter design are examined. On the basis of the single‐stage and two‐stage all‐pass networks, a fully‐differential digital phase shifter with 6‐bit resolution is designed. The digital phase shifter is implemented using a 0.18‐μm complementary metal‐oxide semiconductor process. The chip area is 2.80 × 1.75 mm2. Measurement results show that minimum root‐mean‐square phase error of 2° is achieved from 2.19 to 2.82 GHz, which translates into a bandwidth (BW) of 25%. The average insertion loss is 14.6 dB at the design frequency of 2.4 GHz. Over the entire BW, the return loss is greater than 9.2 dB and the amplitude error is within ±1 dB.

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decreases with increasing R v , however, the stopband attenuation also decreases with increasing R v . This causes a trade-off between these two parameters. In this LTCC BPF design, we wish to achieve the passband insertion loss was lower than 2.0 dB, and the passband return loss was higher than 12 dB. The required stopband attenuation levels are set to values greater than 20 dB above 4.0 GHz to suppress the second harmonic band of the operating frequency. The final prototype element solutions that are chosen to satisfy all the specifications are: C c 5 1.68 pF, L p1 5 0.529 nH, C p1 5 6.86 pF, R 5 255 X. By referring to Figure 4, the U-shaped inductor requires a length of 1.98 mm for having such a specific L p1 value of 0.529 nH.