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The design and implementation of a 77 GHz phase‐locked loop (PLL) for automobile radar system in 90 nm CMOS technology is demonstrated. To enhance the operation frequency range of the voltage‐controlled oscillator in the PLL, reversely tunable LC source degeneration technique is adopted. To improve the frequency locking range of the divide‐by‐3 injection‐locked frequency divider in the PLL, a parallel inductor is used to parallel resonate the parasitic capacitance of the cross‐coupled transistors. In addition, a phase and frequency detector with enhanced D flip flops is used to effectively reduce the dead zone. The PLL consumes only 49.6 mW and exhibits an operation range of 2.4 GHz (76.8∼79.2 GHz) and reference sidebands of <–56 dBc. The chip area of the PLL is only 0.656 mm2 excluding the test pads.

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