Abstract-In current ultra-wideband (UWB) baseband synchronizer approaches, the parallel architecture is used to achieve over 500 MSamples/s throughput requirement. Therefore achieving low power and less area becomes the challenge of UWB baseband design. In this paper, a low-complexity synchronizer combining data-partition-based correlation algorithms and dynamic-threshold design is proposed for orthogonal frequency division multiplexing based UWB system. It provides a methodology to reduce design complexity with an acceptable performance loss. Based on the data-partition algorithms, both single auto-correlator and moving-average-free matched filter are developed with 528 Msample/s throughput for the 480 Mb/s UWB design. Simulation results show the synchronization loss can be limited to 0.8-dB signal-to-noise ratio for 8% system packet-error rate.

Abstract-In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-m single-poly and six-metal CMOS process with a core area of 1.76 1.76 mm 2 , including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s. Index Terms-Fast Fourier transform (FFT), orthogonal frequency division multiplexing (OFDM), ultrawideband (UWB).

A MB-OFDM UWB baseband transceiver with I/Q-mismatch (IQM) calibration and dynamic sampling (DS) is presented. It calibrates IQM by 2dB gain and 20 degree phase errors, releasing IQM tolerance to 10x of existing designs. The DS reduces ADC sampling rate to 1/9 ~ 1/2 of existing designs, resulting in at least 43% ADC power saving. Measured power consumes 31.2mW at 480Mb/s data rate.

Abstract-This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-m single-poly six-metal CMOS process with core area of 4.84 mm 2 . Power dissipation is about 25.2 mW at 20 MHz. Index Terms-DVB-T, fast Fourier transform (FFT), orthogonal frequency division multiplexing (OFDM).

In this paper we propose a low-complexity design concept for COFDM-based wideband system. First the advantage of wideband Coded Orthogonal Frequency Division Multiplexing (COFDM) system containing higher tolerance to carrier frequency offset (CFO) technology has been widely accepted in many communication estimation error is introduced, and hence the synchronizer systems due to both bandwidth efficiency and robustness to channel complexity can be efficiently reduced based on performance distortion. This opens a great of opportunities for SoC society to deal consideration. Second the complexity reduction of QPSK-COFDM with design complexity by exploiting benefits of giga-scale system is presented, the reduced SNR range and phase-processing integration. In this paper, we'll first review the general design can save computations in both symbol timing detection (STD) and concept of COFDM systems and then highlight several key issues in channel equalization, leading to a low-cost and acceptable system SoC realization. Then a system-level design flow by taking into solution. For low power consideration, we suggest an adaptive account both performance indices and hardware complexity will be decoder based on channel conditions, and many redundant operations introduced. Several core modules related to COFDM system will can be reduced. To achieve high-throughput, the parallel decoder also be addressed to see how better solutions can be achieved, architectures that are quite area efficient are presented for Viterbi especially for wireless applications. Finally two case studies on decoders and LDPC decoders. Based on the proposed low-WLAN and OFDM-UWB will be discussed to demonstrate our complexity scheme, the power efficiency of COFDM chips, defined proposals as well as to provide some directions for further research.as power per Mb/s, can be saved to below 1.2 -2.3mW per Mb/s in 0.1 8im CMOS process.