A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling

Yu, Jui-Yuan; Chung, Ching-Che; Liu, Hsuan-Yu; Lin, Yu‐Wei; Liao, Wei; Hsu, Terng-Yin; Lee, Chen‐Yi

doi:10.1109/vlsic.2006.1705397

Cited by 8 publications

(10 citation statements)

References 6 publications

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“…The proposed DSTC and PTCG [10] are evaluated in a multiband OFDM (MB-OFDM)-based ultra-wide-band (UWB) system [12] with a low-density-parity-check (LDPC) code for error correction [13]. The signal bandwidth is 528 MHz with quadrature phase-shift keying (QPSK) and OFDM modulations, and the maximum data rate 480 Mbps is selected in the following simulations.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

“…The resulting PTCG power is 10.9 mW [10] in the 0.13-m standard CMOS process. Table I presents both the performance and the power reduction in this work.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

“…The estimated power reduction is from 160 mW 2 to 70 mW 2 (for both I and Q paths) if the ADC circuits in [14] are taken into account. When the baseband processor power 31.2 mW [10] is included, this reduced sampling rate results in a baseband power saving of mW mW if the ADC [14] is calculated together. Note that the proposed symbol-rate synchronization method requires both the DSTC and PTCG circuits with power consumption of 1.9 and 10.9 mW, respectively.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

“…An all-digital PTCG provides eight clock sampling candidates for phase selection, and outputs a specific one according to the calculated in (10). This PTCG phase-tuning is achieved within a few cycles, and a clock output during this tuning period is glitch-free.…”

Section: Ptcgmentioning

confidence: 99%

“…Unlike multirate sampling methods [1]- [3], this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept [9] is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC [10] for low-power wireless applications.…”

Section: Introductionmentioning

confidence: 99%

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A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

Chung

Lee

2008

IEEE Trans. Circuits Syst. II

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Abstract-This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra power consumed in high-rate operations. The proposed PTCG circuits provide the desired clock phase for optimum sampling to improve system performance. Both the DSTC and the PTCG are evaluated in a multibandt OFDM (MB-OFDM) ultra-wide-band system. Simulation results indicate that the overall system performance is improved by 1.7-dB signal-to-noise ratio at a packet error rate of 8% and the total baseband power is reduced by 40%.Index Terms-Dynamic sample-timing controller (DSTC), orthogonal frequency-division multiplexing (OFDM), phase-tunable clock generator (PTCG), synchronization, ultra-wide-band.

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Section: Simulation and Measurement Resultsmentioning

confidence: 99%

“…The resulting PTCG power is 10.9 mW [10] in the 0.13-m standard CMOS process. Table I presents both the performance and the power reduction in this work.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

Section: Ptcgmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

Chung

Lee

2008

IEEE Trans. Circuits Syst. II

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A MT-CDMA based wireless body area network for ubiquitous healthcare monitoring

Liao

Lee

2006

2006 IEEE Biomedical Circuits and Systems Conference

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Abstract-This paper presents a multi-tone CDMA (MT-CDMA) based system specification for wireless body area network (WBAN) applications. According to the factors of bandwidth, carrier frequency, and electric field intensity defined in wireless medical telemetry service, the function blocks and data format are designed through the considerations of hardware cost, power consumption, and system performance. The design constraints for baseband processor, data conversion, and RF circuits are defined. This work achieves PER=1% and allows interferer distance less than 1.01m. In energy-spectrum efficiency, it provides 3.125 times energy-spectrum product less than the state-of-the-art systems for healthcare applications. Index Terms-CDMA, OFDM, WBAN

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A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications

Chung

Liao

et al. 2007

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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Ubiquitous personal healthcare inspection (uPHI) in a wireless body area network (WBAN) requires continuous signal monitoring up to several days or even longer. To enable cable-free body monitoring with µW biomedical acquisition devices [1,2], a submW wireless transceiver is required for long-term observation. However, existing systems [3,4] have large power dissipation with poor interference-rejection capability, limiting device coexistence and the use of thin-film flexible-batteries. For better operation reliability in an environment with interference, the wireless medical telemetry service (WMTS) constraints defined in [5] are collectively considered. As a result, a multi-tone CDMA (MT-CDMA) baseband processor with a 31-chip spreading code is implemented in a wireless sensor node (WSN) and a central processing node (CPN), respectively, as shown in Fig. 20.5.1, for interference-free and reliable communications in body monitoring. In the battery-capacity-limited WSN, both dynamic and leakage power are optimized, comprising µW-scale power dissipation for extended body-signal monitoring. This power optimization is achieved using a power island approach with the techniques of multi-V t CMOS (MVTCMOS), multiple supply voltage (MSV) domains, and distributed coarse-grain power-gating cells (DCG-PGC), improving the operating duration by 11×. For better system performance, the CPN applies both adaptive I/Q-mismatch calibration (A-IQMC) and dynamic sampling-timing control (DSTC) with phase-tunable clock generation (PTCG) [6] to further improve system SNR by 2.2dB and reduce power dissipation in the ADC by 43.75%. Figure 20.5.1 shows the proposed uPHI-WSN and uPHI-CPN in a coexistence scenario. This transceiver pair may connect with various possible sensor categories and achieves a maximum datarate of 143kb/s for a maximum 10-WSN coexistence, providing large interference-rejection capability and better system reliability. Because uPHI-WSN/CPN communicates with a datarate much higher than a human body's sensor signal rate in this work, a WSN stays asleep for most of time (sleep-phase) and transmits data in a burst mode (active-phase). Therefore, leakage power minimization is emphasized for this long-sleep operation. When an ECG is considered as a body signal source with 16b samples at a sampling rate of 500-samples/s, a 2048×16b SRAM is designed into the WSN. This SRAM size has an optimum leakage saving efficiency, resulting in a 6.96% active-sleep duty cycle. The sampled signals from the sensor are modulated by QPSK with a 16-point IFFT, where the subcarrier allocation follows the conjugate-symmetric rule to further reduce by 50% the DAC and frontend circuit area and power. Then, the baseband signal is transmitted at 5M chip/s. In the CPN on the receiver side, the A-IQMC circuit is provided to compensate for gain and phase signal distortion. Also, a DSTC is applied for best sample timing search with the aid of the PTCG circuit, which provides 5MHz 8-phase evenly spaced clock phases for selection. Each clock phase is sepa...

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A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling

Cited by 8 publications

References 6 publications

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

A MT-CDMA based wireless body area network for ubiquitous healthcare monitoring

A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications

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