The mechanism of single-event gate-rupture in an N-channel VDMOS in a space radiation environment was analyzed. Based on the mechanism, a novel structure of VDMOS for improving single-event gate-rupture is proposed, and the structure is simulated and it is demonstrated that it can improve a VDMOS SEGR threshold voltage by 120%. With this structure, the specific on-resistance value of a VDMOS is reduced by 15.5% as the breakdown voltage almost maintains the same value. As only one mask added, which is local oxidation of silicon instead of an active processing area, the new structure VDMOS it is easily fabricated. The novel structure can be widely used in high-voltage VDMOS in a space radiation environment.

An N-channel VDMOS I-V curve is measured after X-ray radiation under condition of different power dissipation. It is found that the property of new interface traps induced by X-ray radiation of self-annealing VDMOS sample does not conform to existing theory reasonably well. Based on measured data，we advance the viewpoint that the interface trap has current conductive property besides being charged up, and the conduction is assumed to be the generation or recombination current caused by new interface traps, which can not be simply identified quantitatively from the I-V curve.

An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/ m of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/ m and 460 V/ m by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.

A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe layer and forming a p-well by multiple implantation technology, a surface strained Si-channel NMOSFET was fabricated, of which the low field mobility was enhanced by 140%, compared with the bulk-Si control device. Strained NMOSFET and PMOSFET were used to fabricate a strained CMOS inverter based on a SiGe virtual substrate. Test results indicated that the strained CMOS converter had a drain leakage current much lower than the Si devices, and the device exhibited wonderful on/off-state voltage transmission characteristics.

An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches (DTMOS), an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide (BOX). The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide (εox) than that of Si (εSi). Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF (reduced surface field) effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit (HVIC), effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.