High voltage SOI LDMOS with a compound buried layer

Luo, Xiaorong; Gangyi, Hu; Zhou, Kun; Jiang, Yongheng; Wang, Pei; Wang, Qi; Luo, Yong; Zhang, Bo; Li, Zhaoji

doi:10.1088/1674-4926/33/10/104003

J. Semicond.

2012

DOI: 10.1088/1674-4926/33/10/104003

|View full text |Cite

High voltage SOI LDMOS with a compound buried layer

Xiaorong Luo

Hu Gangyi²,

Kun Zhou

et al.

Abstract: An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/ m of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/ m and 460 V/ m by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2013

2014

Publication Types

Select...

Article2

Relationship

Self Cite1

Independent1

Authors

Journals

Cited by 2 publications

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Analytical model for high-voltage SOI device with composite-kdielectric buried layer

Fan¹,

Zhang²,

Luo³

et al. 2013

J. Semicond.

Self Cite

View full text Add to dashboard Cite

An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative permittivity) dielectric buried layer (CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si 3 N 4 and low-k (k D 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage (BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si 3 N 4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional (2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI (LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.

show abstract

Analytical model for high-voltage SOI device with composite-kdielectric buried layer

Fan¹,

Zhang²,

Luo³

et al. 2013

J. Semicond.

Self Cite

View full text Add to dashboard Cite

show abstract

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

Fan¹,

Luo²,

Zhou³

et al. 2014

J. Semicond.

View full text Add to dashboard Cite

A low specific on-resistance (R on; sp / SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on; sp . Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/ m from 48 V/ m of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and R on; sp . Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on; sp by 80% at the same BV.

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

High voltage SOI LDMOS with a compound buried layer

Cited by 2 publications

References 6 publications

Analytical model for high-voltage SOI device with composite-kdielectric buried layer

Analytical model for high-voltage SOI device with composite-kdielectric buried layer

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

Contact Info

Product

Resources

About