Intermetallic compound (IMC) formation is critical for the reliability of microelectronic interconnections, especially for flip chip solder joints. In this article, we investigate the polarity effect of electromigration on kinetics of IMC formation at the anode and the cathode in solder V-groove samples. We use V-groove solder line samples, with width of 100 μm and length of 500–700 μm, to study interfacial IMC growth between Cu electrodes and Sn-3.8Ag-0.7Cu (in wt %) solder under different current density and temperature settings. The current densities are in the range of 103 to 104A∕cm2 and the temperature settings are 120, 150, and 180 °C. While the same types of IMCs, Cu6Sn5 and Cu3Sn, form at the solder∕Cu interfaces independent of the passage of electric current, the growth of the IMC layer has been enhanced by electric current at the anode and inhibited at the cathode, in comparison with the no-current case. We present a kinetic model, based on the Cu mass transport in the sample, to explain the growth rate of IMC at the anode and cathode. The growth of IMC at the anode follows a parabolic growth rule, and we propose that the back stress induced in the IMC plays a significant role. The model is in good agreement with our experimental data. We then discuss the influence of both chemical force and electrical force, and their combined effect on the IMC growth with electric current.

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This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, highcurrent, high-density bump interconnections can be achieved for Si-carrier technology. IntroductionSilicon-carrier System-on-Package (SOP) technology offers much promise for a number of electronic packaging applications [1,2]. Several key technology components are required to enable this technology, including Si through-vias, high-density wiring, and high-density, controlled-collapse chip-connection (C4) interconnects between the silicon chip and silicon carrier (micro-bumps). Micro-bump flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and also enable high-performance signal and power connections. Although small C4 bumps were first fabricated in the 1960's, the packaging industry is only now moving toward bump arrays smaller than standard 100 µm diameter on 200 µm pitch (4-on-8). When combined with high-density wiring in the Sicarrier, high-density interconnections allow increased signal bandwidth between multiple chipsets, with little or no reduction in signal quality. Of equal importance, a high density array of power and ground interconnections allows improvements in power distribution design, especially for applications involving power cycling. Questions remain concerning the viability of fine-pitch bump arrays, particularly for package components with different thermal expansion coefficients (CTE). For Sn-based solders, there is strong formation of brittle intermetallic compounds (IMCs) over time. As the bump size decreases, the ratio of volume to surface area decreases, so the IMCs will constitute a larger portion of the bump.

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The polarity effect of electromigration on intermetallic compound (IMC) formation at the cathode and the anode in solder lines has been investigated. The lines were formed by flowing molten lead-free solder SnAg3.8Cuo.7 into V-grooves etched on (001) silicon wafers, and two copper wires were used as electrodes. The V-groove solder line samples, with width of about lOOpm and length of 600-800p1, were used to study the changes in thickness and morphology of IMC forming at the cathode and the anode in the SnAg3.8Cuo.7/Cu system under different current density and temperature settings. The current densities were in the range of lo3 to lo4 A/cm2 and the temperature settings were 150°C and 180°C. We found that the same IMCs of Cu6Sn5 and Cu3Sn formed at solder/Cu interfaces with or without the passage of electric current. The growth of IMC has been enhanced by electric current at the anode and inhibited at the cathode, comparing with samples without applying current. With a high current density of lo4 A/cm2, the growth of IMC at the anode obeys the parabolic growth rule, which was not predicted previously. We observed that the IMC forming after the initial reflow had a scallop-type morphology, and it transformed into layer-type morphology in current stressing. This is similar to the result of solid state aging without passage of current. However, how it transforms from scallop-type into layer-type morphology is different from the cathode to the anode, which is also different from the way it does in solid state aging. This is because of the polarity effect of electric current and the existence of local current crowding due to the scallop-type morphology of IMC.