Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications

Abstract

This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, highcurrent, high-density bump interconnections can be achieved for Si-carrier technology. IntroductionSilicon-carrier System-on-Package (SOP) technology offers much promise for a number of electronic packaging applications [1,2]. Several key technology components are required to enable this technology, including Si through-vias, high-density wiring, and high-density, controlled-collapse chip-connection (C4) interconnects between the silicon chip and silicon carrier (micro-bumps). Micro-bump flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and also enable high-performance signal and power connections. Although small C4 bumps were first fabricated in the 1960's, the packaging industry is only now moving toward bump arrays smaller than standard 100 µm diameter on 200 µm pitch (4-on-8). When combined with high-density wiring in the Sicarrier, high-density interconnections allow increased signal bandwidth between multiple chipsets, with little or no reduction in signal quality. Of equal importance, a high density array of power and ground interconnections allows improvements in power distribution design, especially for applications involving power cycling. Questions remain concerning the viability of fine-pitch bump arrays, particularly for package components with different thermal expansion coefficients (CTE). For Sn-based solders, there is strong formation of brittle intermetallic compounds (IMCs) over time. As the bump size decreases, the ratio of volume to surface area decreases, so the IMCs will constitute a larger portion of the bump.

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…New defects emerge for 3D chips due to processing steps that did not exist in 2D chips, e.g., wafer thinning, alignment and bonding [100]. Micro-bumps in 3D chips are susceptible to open/bridging defects [101]. New decisions specific to 3D chips also complicate the test flow; there are multiple points at which 3D chips may have to be tested.…”

Silicon carrier for computer systems

“…Area array micro-bumps with nominal diameters of 50 μm and 25 μm and pitch of 100 μm and 50 μm, respectively, have been fabricated (see Figure 3) on the silicon carrier and electrically characterized [16,22]. DC contact resistances equaling 14 mΩ and 17 mΩ were obtained for 50 μm and 25 μm micro-bumps, respectively [22].…”

“…The delay and the losses are expected to reduce as the micro-bump diameter and its respective pad is scaled down to smaller dimensions. Non-uniform current crowding and spreading resistance play a significant role in determining the electrical parasitics of micro-bumps [22] and make it difficult to deduce a simple scalar model that predicts the impact of microbump dimension scaling on its electrical parasitics. Derivation of such model is a subject for future investigation.…”

“…To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Several papers have been published recently by IBM research that introduced the silicon carrier technology for a wide range of twoand three-dimensional product applications and presented detailed descriptions of its key technology enablers [2,5,7,15,16,22]. In its most basic form, the silicon carrier is a silicon substrate that has fine pitch I/Os and high speed wiring on one side, a typical C4 solder bump on the other side and through-vias that connect the two sides (see Figure 1).…”

Integrated microfluidic power generation and cooling for bright silicon MPSoCs

“…There are three major reasons [2,3] for the reduced energy efficiency in current devices: (1) energy required for communication in large chips vis-a-vis computation, (2) losses in power delivery and (3) energy required Mohamed M. Sabry and Arvind Sridhar are authors of equal contributions to this work. This work was partly funded by the EC FP7 STREP GreenDataNet project (no.…”