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We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOScompatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development. Introduction: Among non-volatile memory technologies, Spin-Transfer-Torque (STT) MRAM is seen as a credible candidate to replace SRAM in low level caches due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. This is reflected by major foundries and tool suppliers investing significant R&D resources into embedded MRAM past years. Recently they even started prototyping demonstrators, progressively reaching maturity for mass production [1-5]. However, STT-MRAM

Area-Selective Deposition (ASD) receives increasing attention as a bottom-up approach for nanoelectronic device fabrication. Uptake of ASD is however limited by defects, which manifest as undesired particle growth on the non-growth surface. We demonstrate a defect mitigation solution for Ru ASD on TiN/SiO2 nanopatterns by making use of the size-dependent Ru nanoparticle reactivity. During the initial stages of 1-(ethylbenzyl)-1,4-(ethylcyclohexadienyl)ruthenium and oxygen (EBECHRu/O2) Atomic Layer Deposition on dielectrics, Ru particles are too small to catalytically dissociate oxygen, and their growth is suppressed. This phenomenon creates an ASD process window in which particles can be completely etched while retaining the integrity of the ASD pattern on a TiN growth surface. Decreasing the ALD temperature strongly suppressed defect growth, which can be used to expand the process window for ASD. The ASD process window is confirmed by Self-Focusing Secondary Ion Mass Spectrometry (SF-SIMS) with its low limit of detection while analyzing 10 4 structures simultaneously. No defects are detected for Ru ASD on 36nm TiN/SiO2 patterns by SF-SIMS. We apply the Ru ASD process for bottom-up block patterning and obtain functional hardmask patterns on 300mm wafers. The approach followed in this work can produce defect-free ASD processes for a wide variety of applications.