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This paper propose multichannel random demodulator (MCRD) system, which is block structured sparsity based of multiband signals. It is a kind of compressive sampling system. Each channel of the system firstly multiplies analog signal by a band of random sequence, the product is put into integrator and sampled at a low rate. ADC of this system only need to generate one sample which greatly reduce ADC design complexity. Perfect recovery from the proposed samples is achieved by processing all measurements jointly with orthogonal matching pursuit (OMP) algorithm. The simulation analyzes the compression rate, the number of effective sub-carriers and conversion rate of pseudorandom number generator impact on this system. The results show that MCRD system ensure perfect reconstruction performance for multiband signal that is sampled below the Nyquist rate. Specially, conversion rate impact on system performance would be greatly for higher sampling rate, select the appropriate conversion rates can improve the system performace while reducing system complexity.

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Aiming at the problem that convolutional neural network is difficult to deploy on small embedded devices due to its high complexity and large storage space requirement, this paper propose a convolutional neural network FPGA accelerator architecture based on binarization. Using the gray scale processing, binarization processing, threshold setting to reduce the number of parameters. Designing Parallel structures of convolution kernels, feature maps, and matrix blocks to accelerate. The designed architecture can be deployed on the AX7103 FPGA development platform with limited resources. The experimental results show that the convolutional neural network after parallel acceleration design can achieve a recognition accuracy rate of 98.73% on the premise of reducing the data bit width from 32 bits to 8 bits, the recognition speed is about 0.21 seconds/time.