Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

Recent advances in artificial intelligence (AI) and continuous monitoring of patients using wearable devices have enhanced the accuracy of diagnosing various arrhythmias, from the captured Electrocardiogram (ECG) signals. Achieving high accuracy when using Deep Neural Network (DNN) for ECG classification is accomplished at the cost of compute and memory intensive operations, thus limiting its deployment to devices with high computing capabilities, and makes it unsuitable for wearable edge devices. To facilitate the deployment of deep neural networks on wearable mobile edge devices with limited resources, a lightweight Convolution Neural Network (CNN) model based on the ShuffleNet architecture is proposed and implemented as a solution in this paper. A sliding window of variable stride is used to increase the number of under-represented classes in the database. Moreover, a novel encoding scheme is employed for labelling and training test set samples, allowing the model to detect multiple classes in one ECG segment. A loss function (Focal loss) that proved to be effective when applied for DNN training on an imbalanced dataset was also explored in this work. The proposed model outperformed traditional CNN with 9x less trainable parameters and improved the F1-score by 2%.

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

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Deep learning networks achieve high accuracy for many classification tasks in computer vision and natural language processing. As these models are usually over-parameterized, the computations and memory required are unsuitable for power-constrained devices. One effective technique to reduce this burden is through low-bit quantization. However, the introduced quantization error causes a drop in the classification accuracy and requires design rethinking. To benefit from the hardware-friendly power-of-two (POT) and additive POT quantization, we explore various gradient estimation methods and propose quantization erroraware gradient estimation that manoeuvres weight update to be as close to the projection steps as possible. The clipping or scaling coefficients of the quantization scheme are learned jointly with the model parameters to minimize quantization error. We also apply per-channel quantization on POT and additive POT quantized models to minimize the accuracy degradation due to the rigid resolution property of POT quantization. We show that comparable accuracy can be achieved when using the proposed gradient estimation for POT quantization, even at ultra-low bit precision.