The generation of interface traps at the drain corner during hot-carrier-stress (HCS) in a fully-depleted silicon-on-insulator tunneling field-effect transistor (TFET) was invested and correlated to low-frequency noise performance. The hot carrier damage increases the number of the generated interface traps because hot carriers could gain high kinetic energy to reach the conduction band near the drain region in TFET. Unlike the results of channel-HCS characteristics in MOSFETs, the frequency exponent γ under the same stress voltage conditions in TFET decreased by 21.4%, which was attributed by the generation of interface traps as compared to deeper border traps.

Many attempts have been made to improve the performance of tunneling field-effect transistors (TFETs). Among these, post metal annealing (PMA) can induce enhanced device performance, but its application to TFETs has not been sufficiently explored. In this study, the temperature, time, atmosphere, and pressure conditions for the PMA of a TFET device are optimized. To evaluate if any loss in performance occurred after PMA, we tested the transistors' electrical parameters, specifically their subthreshold slopes and low-frequency noises at 10 Hz. Moreover, the interface trap charge density of the TFETs is extracted as a measure to evaluate their performance. As a result, lower temperatures and shorter PMA times are essential compromises, and the performances were improved under H 2 and D 2 -containing atmospheres. Furthermore, the benefit of having high gas pressures during PMA is noted, because as the number of hydrogen/deuterium atoms increases, more traps-removing surface-gas interactions can occur.

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