Channel current conduction modulation with the spontaneous polarization of ferroelectric films in ferroelectric field-effect transistors (FeFETs) has been widely investigated. Low interface quality and thermodynamic instability owing to the presence of dangling bonds in the conventional ferroelectrics have limited the memory retention and endurance of FeFETs. This, in turn, prevents their commercialization. However, the atomically thin nature of 2D ferroelectric, semiconducting, and insulating films facilitate the achievement of trap-free interfaces as van der Waal heterostructures (vdWHs) to develop FeFETs with long data retention and endurance characteristics. Here, we demonstrate a 2D vdWH FeFET fabricated with ferroelectric CuInP2S6 (CIPS), hexagonal boron nitride (h-BN) as the dielectric, and InSe as the ferroelectric semiconductor channel. The device shows an excellent performance as nonvolatile memory (NVM) with its large memory window (4.6 V at a voltage sweep of 5 V), high drain current on/off ratio (>104), high endurance, and long data retention (>104 s). These results demonstrate the considerable potential of vdWHs for the development of FeFETs for logic and NVM applications.

To address the demands of emerging data-centric computing applications, ferroelectric field-effect transistors (Fe-FETs) are considered the forefront of semiconductor electronics owing to their energy and area efficiency and merged logic-memory functionalities. Herein, the fabrication and application of an Fe-FET, which is integrated with a van der Waals ferroelectrics heterostructure (CuInP 2 S 6 /𝜶-In 2 Se 3 ), is reported. Leveraging enhanced polarization originating from the dipole coupling of CIPS and 𝜶-In 2 Se 3 , the fabricated Fe-FET exhibits a large memory window of 14.5 V at V GS = ±10 V, reaching a memory window to sweep range of ≈72%. Piezoelectric force microscopy measurements confirm the enhanced polarization-induced wider hysteresis loop of the double-stacked ferroelectrics compared to single ferroelectric layers. The Landau-Khalatnikov theory is extended to analyze the ferroelectric characteristics of a ferroelectric heterostructure, providing detailed explanations of the hysteresis behaviors and enhanced memory window formation. The fabricated Fe-FET shows nonvolatile memory characteristics, with a high on/off current ratio of over 10 6 , long retention time (>10 4 s), and stable cyclic endurance (>10 4 cycles). Furthermore, the applicability of the ferroelectrics heterostructure is investigated for artificial synapses and for hardware neural networks through training and inference simulation. These results provide a promising pathway for exploring low-dimensional ferroelectronics.

Ferroelectric two dimensional (2D) materials hold great potential to develop modern miniaturized electronic and memory devices. 2D ferroelectrics exhibiting spontaneous polarization in the out-of-plane direction have been extensively investigated to date, but the loss of their polarization during device operation has been problematic. Although 2D materials with in-plane ferroelectric behavior are more stable against depolarization and thus promising for memory and logic applications, experimental realization of in-plane 2D ferroelectric devices is still scarce. Here, we demonstrate in-plane ferroelectric field effect transistors (FETs) based on a van der Waals heterojunction (vdWHJ), which can perform multibit memory and logic operations. Tin monosulfide (SnS), a 2D material with in-plane ferroelectricity, is partially stacked on top of a semiconducting molybdenum disulfide (MoS2) on a silicon dioxide (SiO2)coated silicon substrate to fabricate vdWHJ FETs in back-gate configuration. Switching of the in-plane polarization direction in the SnS channel modulates the contact barriers at the electrode/SnS and SnS/MoS2 interfaces, thereby creating high resistance states and low resistance states (LRS). The device exhibits a logic transfer characteristic with a high drain current on/off ratio (>106) in LRS and non-volatile memory performance with excellent retention characteristics (extrapolated retention time > 10 years). With exquisite tuning of the channel resistance by SnS polarization and gate bias, we realize multiple states with distinct current levels for multibit memory and logic operations suitable for programmable logic-in-memory applications.