Current metal integration process normally uses hard mask for dry etch process instead of resist to compensate thin resist thickness. As the pattern size becomes smaller, thinner resist thickness is required to get sufficient lithography process window. But this trend increases a risk of systematic hard defect like the metal line bridge in damascene process because of consumption in dielectric material during dry etch process.The sub-32nm patterning with the single exposure is almost on the edge with the 193nm immersion lithography. The smaller lithography CD makes the aerial image contrast worse, which means higher DC level in the unexposed area. This higher DC level, latent image, can sacrifice the resist thickness in the unexposed area and this recessed resist thickness is very harmful for the etch process with the current hard mask which may induce the metal line bridge.Although OPC verification step checks potential hot spot during mask type out flow, there is no predictable method to detect systematic potential defects described above. In this paper, we proposed a new method to detect such potential defects and discussed the performance with wafer result. With this predictable model based search method, the robust patterning process in the sub-32nm node can be developed.