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The successful integration of computers in educational environments depends, to a great extent, on students' attitudes towards them. Widely used computer attitude scales (CASs) focus on the beliefs of typical computer users and do not reveal the more refined attitudes of groups that use computers extensively and develop unique relations with them. This study presents the development and validation of a CAS especially designed for computer science freshmen (CASF). The scale consists of five factors, namely, self-confidence in previous knowledge, hardware usage anxiety, computer engagement, fears of long-lasting negative consequences of computer use and evaluation of positive consequences of computers in personal and social life. Using an analytic computer experience construct, the scale's components were related to multiple aspects of students' computer experience. CASF responses can inform a variety of instructional decisions and classroom management strategies for the first phase of the students' studies.

In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing simulators in order to improve their accuracy. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each case, taking into account the actual operating conditions of each device in the structure. The proposed model incorporates short-channel effects, the influence of body effect and is developed for nonzero transition time inputs. The exact time point when the gate starts conducting is efficiently calculated improving significantly the accuracy of the method. A mapping algorithm for reducing every possible input pattern of a gate to an equivalent signal is introduced and the "weight" of each transistor position in the gate structure is extracted. Complex gates are treated by first mapping every possible structure to a NAND/NOR gate and then by collapsing this gate to an equivalent inverter. Results are validated by comparisons to SPICE and ILLIADS2 for three submicron technologies.

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