Due to the existing problems and delay of 157nm lithography tool, extension of the ArF (193nm) lithography process with resolution enhancement techniques (RET) should be considered for the 65nm generation lithography and beyond. The mature double-exposure lithography process based on dark-field alternating phase-shift mask (PSM) is one of the promising RET candidates, which is proven to be one of the production-ready strong phase-shifting techniques for current and future IC generations.In this paper, poly gate patterning with the minimum pitch of 160nm has been demonstrated with high numeric aperture (NA) and small partial coherence of ArF lithography along with a dark-field alternating PSM. For poly gate patterning of 65nm generation, optimum illumination settings are found for minimum pitch of 160nm. Through-pitch common process windows for gates with 65nm after-development-inspection (ADI) critical dimension (CD) at minimum pitch of 160nm can be reached larger than 0.30um depth of focus (DOF), which can be used for 65nm node production. Through-pitch proximity can be compensated by optical proximity correction (OPC). Line edge roughness (LER) can be improved a little by this dark-field alternating PSM technique. LER is found of strong aerial image contrast dependency. Shifter width is also chosen as optimum value to obtain the largest process windows and minimize the phase conflicts. 193nm Hi-NA or liquid immersion lithography is suggested to push the alternating PSM resolution limitation.

In our previously published work, we investigated alternating-aperture PSM image intensity imbalance as function of various mask and optical parameters using rigorous electro-magnetic field (EMF) simulations. 1 Results suggested that the imbalance could be effectively compensated through application of an optimized combination of undercut and a constant phase-shifter bias. In the effort of development and implementation of a production-ready image imbalance correction methodology, it is important to validate the accuracy of simulation-based predictions through correlation of results to experimental data. For this purpose, a test reticle containing various mask parameters as variables was designed and manufactured. The experimental data was obtained from SEM measurements of the exposed wafers, and results were compared to rigorous EMF simulation data. Based on results obtained, we propose and validate an image imbalance correction methodology to be implemented within the framework of the PSM -OPC manufacturing flow.

Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrin k and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists' glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.

As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution required and various double patterning techniques have become the main stream prior to the availability of EUV lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch (LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially for topography issues induced by the 1 st mask patterning with the 2 nd mask exposure. In this paper, laser parameters, topography issues with the 2 nd mask exposure, and SMO effects on CD performances are described in terms of the proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic performance was calculated and used to illustrate the importance of well-controlled laser performance parameters. Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.

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